HEF4011BT,653 NXP Semiconductors, HEF4011BT,653 Datasheet - Page 6

• Manufacturer Part Number: HEF4011BT,653
• Description: IC GATE NAND QUAD 2INPUT SO14
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4011BT,653

• Number Of Circuits: 4
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Type: NAND Gate
• Number Of Inputs: 2
• Current - Output High, Low: 2.4mA, 2.4mA
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: HEF4000
• High Level Output Current: - 3.6 mA
• Low Level Output Current: 3.6 mA
• Propagation Delay Time: 20 ns
• Supply Voltage (max): 15.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logical Function: NAND
• Number Of Elements: 4
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Operating Temp Range: -40C to 125C
• Package Type: SO
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Automotive
• Quiescent Current: 1uA
• Operating Supply Voltage (max): 15V
• Operating Supply Voltage (min): 3V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933372640653; HEF4011BTD-T; HEF4011BTD-T

NXP Semiconductors
12. Waveforms
Table 9.
Table 10.
HEF4011B
Product data sheet
Supply voltage
V
5 V to 15 V
Supply voltage
V
5 V to 15 V
Fig 4.
Fig 5.
DD
DD
Measurement points are given in
Logic levels: V
Propagation delay, output transition time
Test data is given in
Definitions for test circuit:
DUT = Device Under Test.
C
R
Test circuit for measuring switching times
L
T
Measurement points
Test data
= load capacitance including jig and probe capacitance.
= termination resistance should be equal to the output impedance Z
OL
and V
Table
Input
V
V
OH
I
SS
10.
are typical output voltage levels that occur with the output load.
or V
output
DD
input
Table
Input
V
0.5V
All information provided in this document is subject to legal disclaimers.
G
M
V
V
0 V
OH
OL
V
9.
DD
I
V
10 %
I
Rev. 4 — 30 March 2011
90 %
R T
V
90 %
M
t
DUT
V
r
V
DD
10 %
M
t
PHL
t
t
 20 ns
THL
r
, t
f
V
O
C L
o
of the pulse generator.
001aag182
t
f
001aag197
t
PLH
t
TLH
Output
V
0.5V
M
DD
Load
C
50 pF
Quad 2-input NAND gate
L
HEF4011B
© NXP B.V. 2011. All rights reserved.
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