sii1161 Silicon image, sii1161 Datasheet - Page 18

• Manufacturer Part Number: sii1161
• Description: Panellink Receiver
• Manufacturer: Silicon image

Actual setup and hold times can be derived from the clock period at the operating frequency of interest. Clock
duty cycle must also be taken into account when calculating setup and hold times.
Table 8 shows the calculations required for determining setup and hold timings using the clock period T
specific to the clock frequency when OCK_INV=1. The setup and hold times apply to DE, VSYNC, HSYNC and
Data output pins, as long as the appropriate T
shows calculated setup and hold times for commonly used ODCK frequencies.
SiI-DS-0096-D
Symbol
T
T
SU
HD
Data Setup Time to ODCK
=T
Data Hold Time from ODCK
=T
+ T
-T
ODCK
CK2OUT
ODCK
Table 8. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=1
CK2OUT
*T
* (1 - T
{max}
DUTY
{min}
Parameter
{min)
DUTY
Hold Time from ODCK:
{max})
Setup Time to ODCK:
CK2OUT
Frequency
82.5 MHz
82.5 MHz
165 MHz
165 MHz
25 MHz
25 MHz
T
ODCK
value is used for the calculation in each case. The table also
T
ODCK
14
* (1 - T
*T
DUTY
T
40 ns
12 ns
40 ns
12 ns
DUTY
6 ns
6 ns
ODCK
{min} - T
{max}) + T
T
CK2OUT
CK2OUT
=1.2
=0.0
Max
Min
CK2OUT
(data)
{max}
{min}
SiI 1161 PanelLink Receiver
=40*40% - 1.2 = 14.8ns
=40*40% - 0.0 = 16.0ns
=12*40% - 1.2 = 3.6ns
=12*40% - 0.0 = 4.8ns
=6*40% - 1.2 = 1.2ns
=6*40% - 0.0 = 2.4ns
Result
Data Sheet
ODCK