sii1161 Silicon image, sii1161 Datasheet - Page 23

• Manufacturer Part Number: sii1161
• Description: Panellink Receiver
• Manufacturer: Silicon image

SiI 1161 PanelLink Receiver
Data Sheet
Pin Descriptions
Output Pins
Pin Name
Differential Signal Data Pins
Pin Name
EXT_RES
HSYNC
VSYNC
QO23-
QE23-
ODCK
RXC+
RX0+
RX1+
RX2+
CTL1
CTL2
CTL3
RXC-
RX0-
RX1-
RX2-
QO0
QE0
DE
Diagram
Diagram
SiI 1161
SiI 1161
Pin #
Pin #
See
See
Pin
Pin
44
46
48
47
40
41
42
90
91
85
86
80
81
93
94
96
Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
Analog Impedance Matching Control. An external 390Ω resistor must be connected between AVCC
Type
Type
Out
Out
Out
Out
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode
and to the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock
mode. During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pull-
down device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is not powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
and this pin.
19
Description
Description
SiI-DS-0096-D