sii1161 Silicon image, sii1161 Datasheet - Page 9

• Manufacturer Part Number: sii1161
• Description: Panellink Receiver
• Manufacturer: Silicon image

SiI 1161 PanelLink Receiver
Data Sheet
General AC Specifications
Notes
DC and AC parameters specific to the operating mode of the SiI 1161 are listed on the following pages.
The output pin timing specifications are dependent on the selection of output drive capability. Specifications are
listed for two modes: SiI 161B mode, which requires no I
optimization of input data recovery and output drive using I
most suited to their board-level requirements.
Symbol
T
T
T
T
T
T
T
T
T
T
T
R
R
T
F
F
I2CDVD
CLKPD
CLKPU
T
RESET
1.
2.
3.
4.
5.
6.
7.
CTLW
DUTY
DPS
CCS
PDL
HSC
FSC
IJIT
CIP
CIP
CIP
CIP
ST
Guaranteed by design.
Jitter defined per DVI 1.0 Specification, Section 4.6 – Jitter Specification.
Jitter measured with Clock Recovery Unit per DVI 1.0 Specification, Section 4.7 – Electrical Measurement
Procedures.
Measured with transmitter powered down.
All Standard Mode I
Control pulses include HSYNC, VSYNC, CTL1, CTL2 and CTL3. Pulses narrower than this minimum width
specification are filtered out in the receiver and will not be seen at the output pins.
ODCK duty cycle is independent of the differential input clock duty cycle and the transmitter IDCK duty cycle.
Intra-Pair (+ to -) Differential Input Skew
Channel to Channel Differential Input Skew
Worst Case Differential Input Clock Jitter
tolerance
ODCK Cycle Time (one pixel per clock)
ODCK Frequency (one pixel per clock)
ODCK Cycle Time (two pixels per clock)
ODCK Frequency (two pixels per clock)
Output Clock Duty Cycle
Delay PD# / PDO# Low to high-Z outputs
Link disabled (DE inactive) to SCDT low
Link enabled (DE active) to SCDT high
Delay from RXC+ Inactive to high-Z outputs
Delay from RXC+ active to data active
ODCK high to even data output
SDA Data Valid Delay from SCL high to low
transition
Control Pulse Width
PD# Signal Low Time required for a valid I
reset
2
C (100kHz and 400kHz) timing requirements are guaranteed by design.
Parameter
Table 2. General AC Specifications
2
C
165MHz
165MHz
65 MHz
112 MHz
165 MHz
one pixel per
clock
two pixels per
clock
C
5
Conditions
L
= 400pf
2
2
C initialization; and SiI 1161 mode, which allows for
C programming. Designers should choose the mode
12.5
40%
Min
25
12
10
6
4
2
Typ
0.25
Max
82.5
60%
245
465
270
182
165
100
700
40
80
10
50
10
10
4
DE edges
Units
MHz
MHz
R
R
ms
ps
ns
ps
ps
ps
ns
ns
ns
µs
µs
ns
µs
SiI-DS-0096-D
CIP
CIP
Notes
2,3
1
1
1
1
1
1
7
1
1
1
1
5
6
1