ch7007a Chrontel, ch7007a Datasheet
ch7007a
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ch7007a Summary of contents
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... PC solution using the primary display. LINE YUV-RGB CONVERTER MEMORY TRUE SCALE SCALING & DEFLICKERING ENGINE SYSTEM CLOCK PLL RESET* XCLK* H Figure 1: Functional Block Diagram CH7007A TM D ESCRIPTION solutions. All features are NTSC/PAL TRIPLE ENCODER DAC & FILTERS TIMING & SYNC ...
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... CHRONTEL ESCRIPTIONS 3.1 Package Diagram D[1] 1 D[2] 2 D[ DVDD D[5] 6 D[6] 7 DGND] 8 D[7] 9 D[ CHRONTEL CH7007 Figure 2: 44-Pin LQFP 201-0000-002 CH7007A XI/FIN 31 AVDD 30 DVDD 29 RESET* 28 DGND VDD 24 ISET 23 GND Rev. 2.95, 6/24/2004 ...
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... In SCART mode, this pin outputs the red signal. Current Set Resistor Input This pin sets the DAC current. A 360 ohm resistor should be connected between this pin and GND using short and wide traces. CH7007A 3 ...
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... Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Digital Supply Voltage Digital Ground DAC DAC Supply Voltage PLL Supply Voltage PLL Ground I/O SUPPLY VOLTAGE Digital supply voltage for the P-OUT CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... Rev. 2.95, 6/24/2004 Color Space and Depth RGB 15-bit RGB 16-bit YCrCb (24-bit) Cb,Y0,Cr,Y1,(CCIR656 style) RGB 24 8-8-8 over two words - ‘C’ version RGB 24 8-8-8 over two words - ‘I’ version CH7007A Format Reference 5-5-5 over two bytes 5-6-5 over two bytes 5 ...
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... When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d. Figure 4: Non-multiplexed Data Transfers Table 3. RGB 8-bit Multiplexed Mode IDF# Format Pixel# P0a Bus Data D[7] G0[2] D[6] G0[1] D[5] G0[0] D[4] B0[4] D[3] B0[3] D[2] B0[2] D[1] B0[1] D[0] B0[0] 6 SAV (DSEN=0) P0a 7 RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] CH7007A . P0b P1a P1b P2a P2b 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... YCrCb 8-bit P0b P1a P1b Y0[7] Cr0[7] Y1[7] Y0[6] Cr0[6] Y1[6] Y0[5] Cr0[5] Y1[5] Y0[4] Cr0[4] Y1[4] Y0[3] Cr0[3] Y1[3] Y0[2] Cr0[2] Y1[2] Y0[1] Cr0[1] Y1[1] Y0[0] Cr0[0] Y1[0] 9 YCrCb 8-bit P0b P1a P1b S[0] CH7007A 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[7] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] P2a P2b P3a P3b Cb2[7] Y2[7] Cr2[7] Y3[7] Cb2[6] Y2[6] Cr2[6] Y3[6] Cb2[5] Y2[5] Cr2[5] ...
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... When genlocked, the CH7007 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set. 8 CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... CH7007A Pixel Horizontal Vertical Clock Total Total 24.671 784 525 28.196 784 600 30.210 800 630 39.273 1040 630 43.636 1040 700 47.832 1064 750 21.147 840 420 26.434 840 525 30 ...
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... Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the serial port interface circuits are disabled. This places the CH7007 in its lowest power consumption mode. CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... The composite luminance and chrominance frequency response is depicted in Figure 5 through 7. 201-0000-002 Rev. 2.95, 6/24/2004 TM , Inc. and the customer. Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video YCV YSV[1:0], YPEAK = 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 0.81 1.93 2.87 1.93 0.99 2.36 3.52 2.36 1.27 3.03 4.51 3.03 1.57 3.75 5.59 3.75 1.07 2.56 3.81 2.56 1.33 3.17 4.72 3.17 1.13 2.69 4.01 2.69 1.42 3.39 5.05 3.39 0.95 2.28 3.39 2.28 1.19 2.84 4.24 2.84 1.36 3.25 4.84 3.25 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 1.42 3.39 5.05 3.39 0.98 2.35 3.50 2.35 1.13 2.70 4.02 2.70 1.21 2.89 4.31 2.89 1.18 2.82 4.20 2.82 1.44 3.44 5.13 3.44 1.56 3.73 5.56 3.73 1.18 2.82 4.20 2.82 1.31 3.13 4.66 3.13 1.44 3.43 5.11 3.43 1.08 2.58 3.85 2.58 1.08 2.58 3.85 2.58 CH7007A S-Video YSV[1:0], YPEAK = 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 2.87 4.46 2.19 3.79 3.52 5.46 2.68 4.64 4.51 7.00 3.44 5.95 5.59 8.68 4.27 7.38 3.81 5.92 2.91 5.04 4.72 7.33 3.60 6.23 4.01 6.22 3.06 5.29 5.05 7.84 3.85 6.67 3.39 5.26 2.59 4.48 4.24 6.58 3.23 5.59 4.84 7.52 3.70 6.39 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 5.05 7.84 3.85 6.67 3.50 5.43 2.67 4.62 4.02 6.24 3.07 5.30 4.31 6.68 3.29 5.68 4.20 6.53 3.21 5.55 5.13 7.97 3.92 6.77 5.56 8.63 4.24 7.34 4.20 6.52 3.20 5.54 4.66 7.24 3.56 6.16 5.11 7.94 3.90 6.75 3.85 5.97 2.94 5.08 3.85 5.97 2.94 5.08 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97 11 ...
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... Luminance and Chrominance Filter Options (continued < > i YCVdB Figure 5: Composite Luminance Frequency Response (YCV = 0) < > SVdB Figure 6: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... Luminance and Chrominance Filter Options (continued -12 12 -18 18 < > i UVfirdB n <i> (UVfirdB ) n -24 24 -30 30 - Figure 7: Chrominance Frequency Response 201-0000-002 Rev. 2.95, 6/24/2004 n CH7007A ...
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... Active video and black ( times vary greatly due to different scaling ratios used in different modes. Black times (F and H) vary with position controls. 14 Level (mV) NTSC PAL 1.49 - 1.51 287 300 4. 0.59 - 0.61 287 300 2.50 - 2.53 287 300 1.55 - 1.61 287 300 0.00 - 7.50 340 300 37.66 - 52.67 340 300 0.00 - 7.50 340 300 201-0000-002 CH7007A Duration (uS) NTSC PAL 1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67 Rev. 2.95, 6/24/2004 ...
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... CH7007A 271 272 273 274 275 268 268 270 270 271 271 ...
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... FIE LD 3 625 FIE LD 4 312 313 314 315 316 317 4 3 ° ° ° CH7007A 318 319 320 321 322 323 318 319 320 321 322 323 201-0000-002 ...
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... Green 18.98 Magenta 15.62 Red 13.49 Blue 10.14 Blank/ Black 8.00 Sync 0.00 Figure 12: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-002 Rev. 2.95, 6/24/2004 Color bars: V 1.000 0.925 0.801 0.726 0.608 0.533 0.415 0.340 0.287 0.000 Color bars: V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300 0.000 CH7007A 17 ...
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... Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 14: PAL C (Chrominance) Video Output Waveform (DACG = 1) 18 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... Color/Level V Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 16: Composite PAL Video Output Waveform (DACG = 1) 201-0000-002 Rev. 2.95, 6/24/2004 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7007A 19 ...
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... The devices retains all register states. Regarding the CH7007 registers programming, please see Application Note AN-47 for details. 20 CH7007A 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... Controls for the PLL and memory sections 21H 5 Control of CIV value 21H - 8 each Readable register containing the calculated 24H subcarrier increment value 25H 8 Device version number 26H - 30 Reserved for test (details not included herein) 29H 3FH 6 Current register being addressed CH7007A Functional Summary 21 ...
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... CIV4 CIV3 VID5 VID4 VID3 TS1 TS0 RSA MS2 MS1 MSO YLM5 YLM4 YLM3 CLM5 CLM4 CLM3 AR5 AR4 AR3 CH7007A Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FY0 FT1 FT0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 SAV1 ...
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... CH7007A Symbol: DMR Address: 00H Bits SR2 SR1 SR0 R/W R/W R Output Pixel Clock Format Scaling (MHz) PAL 5/4 21 ...
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... CVBW Symbol: R/W R/W Type NTSC PAL FC1 FC0 FY1 R/W R/W R CBW1 CBW0 YPEAK R/W R/W R/W CH7007A 11 NTSC-J Symbol: FFR Address: 01H Bits FY0 FT1 FT0 R/W R/W R Symbol: VBW Address: 03H Bits YSV1 YSV0 YCV R/W R/W R/W 201-0000-002 Rev. 2.95, 6/24/2004 ...
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... Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1 causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter. 201-0000-002 Rev. 2.95, 6/24/2004 CH7007A ...
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... Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK Reserved IDF3 R/W R Description Reserved MCP XCM1 R/W R/W R CH7007A Symbol: IDF Address: 04H Bits IDF2 IDF1 IDF0 R/W R/W R µ Symbol: CM Address: 06H Bits XCM0 ...
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... SAV5 SAV4 SAV3 R/W R/W R CH7007A Symbol: SAV Address: 07H Bits SAV2 SAV1 SAV0 R/W R/W R Symbol: PO Address: 08H Bits SAV8 HP8 VP8 ...
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... BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7007A Symbol: BLR Address: 09H Bits BL2 BL1 BL0 R/W R/W R Symbol: HPR Address: 0AH Bits HP2 HP1 HP0 R/W R/W R Symbol: VPR Address: 0BH ...
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... Most pins and circuitry are disabled (except for the buffered clock outputs which are limited to the 14MHz output and VCO divided outputs). S-Video DACs are powered down. All circuits and pins are active. All circuitry is powered down except serial port interface circuit. CH7007A Symbol: SPR Address: 0DH Bits ...
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... From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0 1.235V). If the measured voltage is below this threshold threshold CH7007A Symbol: CDR Address: 10H Bits CVBST SENSE ...
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... Normal Contrast = (17/16)*(Y -0) out in = (9/8)*(Y -0) out in = (5/4)*(Y -0) out in = (3/2)*(Y -0) = Enhances White out 128 160 192 Reserved Reserved R/W R CH7007A 224 256 Symbol: MNE Address: 13H Bits R/W R/W R ...
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... PAL, 3 800X600, NTSC, 5:6 108 3 23 800X600, NTSC, 3 800X600, NTSC, 7: 720X576, PAL, 1 720X480, NTSC, 1:1 190 13 20 CH7007A Symbol: PLLM Address: 14H Bits R/W R/W R Symbol: PLLN Address: 15H Bits R/W R/W ...
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... TV horizontal sync (for test use only) 111 TV vertical sync (for test use only) Table 23. K3 Selection SHF[2:0] K3 000 2.5 010 3.5 011 4 100 4.5 101 5 110 6 111 7 201-0000-002 Rev. 2.95, 6/24/2004 SHF2 SHF1 SHF0 R/W R/W R CH7007A Symbol: BCO Address: 17H Bits SCO2 SCO1 SCO0 R/W R/W R ...
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... FSCI# R/W NTSC “No Dot Crawl” 763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 516,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 428,556,645 569,410,927 CH7007A Symbol: FSCI Address: 18H - 1FH Bits each FSCI# FSCI# FSCI# R/W R/W R/W PAL-M “Normal Dot Crawl” 762,524,467 622,468,953 573,798,541 ...
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... GPIO pins. 201-0000-002 Rev. 2.95, 6/24/2004 PAL-N “Normal Dot Crawl” 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942 DVDD2 P-OUTP FSCI19 R/W R/W R CH7007A Symbol: Address: 1BH Bits FSCI18 FSCI17 FSCI16 R/W R/W R ...
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... Mode is shown below. PLLCPI The default value should be used DSM DSEN FSCI15 R/W R/W R PLLCPI PLLCAP PLLS R/W R/W R CH7007A Symbol: Address: 1CH Bits FSCI14 FSCI13 FSCI12 R/W R/W R Symbol: PLLC Address: 20H Bits PLL5VD PLL5VA MEM5V R/W R/W R/W ...
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... CHRONTEL Table 26. PLL Capacitor Setting Mode 201-0000-002 Rev. 2.95, 6/24/2004 PLLCAP Value CH7007A 37 ...
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... CIV24 CIV# CIV# CIV VID5 VID4 VID3 CH7007A Symbol: CIVC Address: 21H Bits CIVH1 CIVH0 ACIV R/W R/W R Symbol: CIV Address: 22H - 24H Bits CIV# CIV# CIV ...
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... CHRONTEL Address Register Bit Reserved Reserved Symbol: Type: Default: The Address Register points to the register currently being accessed. 201-0000-002 Rev. 2.95, 6/24/2004 AR5 AR4 AR3 R/W R/W R CH7007A Symbol: AR Address: 3FH Bits AR2 AR1 AR0 R/W R/W R ...
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... DVDD2 (1.8V) current (15pF load) Total power down current 40 Min - 0.5 1 GND - 0 Min 4.75 4.75 3.1 1.7 3 Min Typ 9 9 33.89 105 45 4 0.06 CH7007A Typ Max Units 7.0 V VDD + 0.5 V Indefinite Sec °C 85 150 °C °C 150 °C 260 245 °C °C 225 The temperature 5V can 0. Typ Max Units 5 ...
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... Low Voltage Notes refers to all digital pixel and clock inputs DATA refers to pixel data output. P-OUT 201-0000-002 Rev. 2.95, 6/24/2004 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref+0.25 GND-0.5 IOL = - 400 µA 2.8 IOL = 3.2 mA CH7007A Typ Max Unit 0.4 V VDD + 0.5 V 1.4 V DVDD+0.5 V Vref-0. 0 ...
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... Hold time: t4 Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7007A t4 t3 P0a P0b P1a P1b P2a P2b t5 t3 Min Typ Max Unit 1 ...
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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load 201-0000-002 Rev. 2.95, 6/24/2004 PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7007A P0a P0b P1a P1b P2a P2b t5 t3 Min Typ ...
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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load Hold time: t6 P-OUT to HSYNC, VSYNC delay t7 (P-OUT=VREF) to (XCLK =XCLK*) delay PIXELS 1 VGA Line CH7007A P0a P0b P1a P1b P2a t3 Min Typ Max 1.7 3.6 DVDD2 - 0 ...
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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-002 Rev. 2.95, 6/24/2004 SYMBOL 0.30 1.35 0.05 0.80 0.40 1.45 0.15 0.012 0.0531 0.00197 0.031 0.016 0.0571 0.0059 CH7007A LEAD E .004 0.50 0° 1.016 0.75 0.17 7° 0.0197 0° 0.040 0.0295 0.0067 7° 45 ...
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... Disclaimer ORDERING INFORMATION Package type Number of pins LQFP 44 LQFP, Tape&Reel 44 LQFP, Lead Free 44 LQFP, Lead Free, 44 Tape&Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7007A Voltage supply 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 201-0000-002 Rev. 2.95, 6/24/2004 ...