ch7007a Chrontel, ch7007a Datasheet - Page 5

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4. D
The CH7007 digital video interface provides a flexible digital interface between a computer graphics
controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output
function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are
subject to programmable control through the CH7007 register set. This interface can be configured as 8
or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit
color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of
the input data format modes is as follows:
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7007 can operate in either master (the CH7007 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or
3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7007 will
automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7007. In the case of CCIR656 style input (IDF = 9), embedded sync may also be
used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first
value of the (Total Pixels/line x Total Lines/Frame) column of Table 13 on on page 23 (Display Mode Register 00H
description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync
signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table 13
on page 24.
Master Clock Mode: The CH7007 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal
will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel
data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits
back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the
specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the
leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus
horizontal sync width, will determine when the chip will begin to sample pixels.
201-0000-002
Table 2. Input Data Formats
Width
12-bit
12-bit
8-bit
8-bit
8-bit
Bus
IGITAL
V
Rev. 2.95, 6/24/2004
IDEO
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
Transfer Mode
I
NTERFACE
Color Space and Depth
YCrCb (24-bit)
RGB 15-bit
RGB 16-bit
RGB 24
RGB 24
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
Cb,Y0,Cr,Y1,(CCIR656 style)
5-5-5 over two bytes
5-6-5 over two bytes
Format Reference
CH7007A
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