ch7019 Chrontel, ch7019 Datasheet - Page 10

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.2
2.2.1
Multiplexed pixel data inputs to the CH7019 through D1[11:0] or D2[11:0] using data transfer method A or B described
in 3.1. Received data is formatted and sent through an internal data bus P1[23:0] to TV encoder or directly to the TV
DACs, or through bus P2[23:0] to the LVDS data path. The multiplexed input data formats are (IDF1[3:0]=0,1,2,3 and
4 for D1 and IDF2[3:0]=0,1,2,3 and 4 for D2):
IDFx
0
1
2
3
4
For multiplexed input data formats, data can be latched from the graphics controller by either rising only or falling only
clock edges, or by both rising and falling clock edges. The MCPx bits select the rising or the falling clock edge, where
rising refers to rising edge on the XCLKx signals and falling edge on the XCLKx* signals. The multiplexed input data
formats are shown in Figure 7 below. The input data bus Dx[11:0], where x can be either 1 or 2, transports a 12-bit or
8-bit multiplexed data stream containing either RGB or YcrCb formatted data. The input data rate is 2X the pixel rate
and each pair of Pn values (e.g.; P0a and P0b) contains a complete pixel encoded as shown in the Tables 3 to 6 below
and can be placed onto one or both of the internal pixel buses Py[23:0], where y equals 1 or 2. It is assumed that the first
clock cycle following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if
an active pixel was present immediately following the horizontal sync. When the input is a YCrCb data stream the
color-difference data will be transmitted at half the data rate of the luminance data with the sequence being set as Cb0,
Y0, Cr0, Y1, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte
refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode,
and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats, and 16 for Y and 128
for CrCb in YCrCb formats.
10
Input Data Formats
Description
RGB 8-8-8 (2x12-bit)
RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit)
RGB 5-6-5 (2x8bit)
RGB 5-5-5 (2x8-bit)
YCrCb 8-8 (2x8-bit)
12-Bit Multiplexed Data Formats
Hx
XCLKx
(2X)
XCLKx
(1X)
DEx
Dx[11:0]
Figure 7: 12-bit Multiplexed Input Data Formats (IDFx = 0,1,2,3,4)
SAV
P0a
P0b
P1a
201-0000-048
P1b
P2a
P2b
Rev. 2.4, 12/18/2006
CH7019B