ch7019 Chrontel, ch7019 Datasheet - Page 57

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
GPIO Invert
C5GP[2:0] (bits 7-5) of register GPIOINV define the GPIO C5 Control bits [5:4]. The entire bit field is made up of these
bits C5GP[2:0] plus C5GP[5:3] contained in the LVDS Encoding 2 register (65h, bits 7-5). Refer to the description of
the LVDSE2 register (address 65h) for more information.
Active Pixel Input & Line Output
STFDS[1:0] (bits 8-7) of register APILO control FLD2 and FLD1 output to a VGA controller. These bits can be
programmed to be a TV field output from the TV encoder. These outputs are tri-stated upon power up. A value of ‘1’
allows FLD output. STFDS0 controls FLD1 and STFDS1 controls FLD2 output. Note that the FLDx pins must first be
enabled using the STFDENx bits located in register 10h, bits 7-6.
201-0000-048
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
X2CMD3
STFDS1 STFDS0
C5GP2
R/W
R/W
Rev. 2.4,
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
7
7
Table 33: Delay applied to XCLK2 before latching input data D2
X2CMD2
C5GP1
12/18/2006
R/W
R/W
6
0
6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X2CMD1
Reserved Reserved Reserved Reserved Reserved Reserved
C5GP0
R/W
R/W
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
5
0
5
0
X2CMD0
Reserved Reserved Reserved Reserved Reserved
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
0
4
1
Adjust phase of Clock relative to Data
0 unit, XCLK2 ahead of Data
1 unit, XCLK2 ahead of Data
2 unit, XCLK2 ahead of Data
3 unit, XCLK2 ahead of Data
4 unit, XCLK2 ahead of Data
5 unit, XCLK2 ahead of Data
6 unit, XCLK2 ahead of Data
7 unit, XCLK2 ahead of Data
0 unit, XCLK2 behind Data
1 unit, XCLK2 behind Data
2 unit, XCLK2 behind Data
3 unit, XCLK2 behind Data
4 unit, XCLK2 behind Data
5 unit, XCLK2 behind Data
6 unit, XCLK2 behind Data
7 unit, XCLK2 behind Data
R/W
R/W
3
1
3
1
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
R/W
R/W
2
0
2
0
R/W
R/W
GPIOINV
5Ch
3
APILO
60h
2
1
1
1
1
CH7019B
R/W
R/W
0
0
0
0
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