ch7019 Chrontel, ch7019 Datasheet - Page 51

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
POUTP (bit 0) of register GPIO controls the polarity of the P-Out signal. A value of ‘0’ does not invert the clock at the
output pad.
POUTE (bit 1) of register GPIO enables the P-Out signal. A value of ‘1’ drives the P-Out clock signal out of the
P-Out pin. A value of ‘0’ disables the P-Out signal.
GPIOL[1:0] (bits 5-4) of register GPIO define the GPIO Read or Write Data bits [1:0]. The entire bit field is made up of
these bits GPIOL[1:0] plus GPIOL[5:2] contained in the GPIO Data register (address 6Dh, bits 3-0). Refer to the
description of the GPIOD register (6Dh) for more information.
GOENB[1:0] (bits 7-6) of register GPIO define the GPIO Direction Control bits [1:0]. The entire bit field is made up of
these bits GOENB[1:0] plus GOENB[5:2] contained in the GPIO Direction Control register (address 6Eh, bits 3-0).
Refer to the description of the GPIODC register (6Eh) for more information.
Input Data Format Register
IDF1[2:0] (bits 2-0) of register IDF select the input data format for the D1 input. The entire bit field, IDF1[3:0], is
comprised of this register IDF1[2:0] plus IDF3 contained in the DAC Control Register (21h, bit5). See Section 3.2 for a
listing of available formats.
HSPTV (bit 3) of register IDF controls the horizontal sync polarity for TV. A value of ‘0’ defines the horizontal sync to
be active low, and a value of ‘1’ defines the horizontal sync to be active high.
VSPTV (bit 4) of register IDF controls the vertical sync polarity for TV. A value of ‘0’ defines the vertical sync to be
active low, and a value of ‘1’ defines the vertical sync to be active high.
SYOTV (bit 5) of register IDF controls the sync direction for TV. A value of ‘0’ defines sync to be input to the CH7019,
and a value of ‘1’ defines sync to be output from the CH7019. The CH7019 can only output sync signals when operating
as a VGA to TV encoder, not when operating as an LVDS transmitter.
DES (bit 6) of register IDF signifies when the CH7019 is to decode embedded sync signals present in the input data
stream instead of using the H and V pins. This feature is only available for input data formats # 4, 6 or 7. A value of ‘0’
selects the H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
IBS1 (bit 7) of register IDF selects the data and clock input buffer type for the D1 data, this bit has to set to “1” (differential
clock and data type).
201-0000-048
DEFAULT:
SYMBOL:
TYPE:
BIT:
IBS1
R/W
Rev. 2.4,
7
0
DES
R/W
12/18/2006
6
0
SYOTV
R/W
5
0
VSPTV
R/W
4
0
HSPTV
R/W
3
0
Symbol:
Address:
Bits:
IDF12
R/W
2
0
IDF11
R/W
IDF
1Fh
8
1
0
CH7019B
IDF10
R/W
0
0
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