ch7019 Chrontel, ch7019 Datasheet - Page 43

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
TV PLL Control Register
PLLCAP (bit 0) of register TPC controls the TV PLL loop filter capacitor. A recommended listing of PLLCAP settings
versus mode is given in Table 24 below.
Mode
PLLCPI (bit 1) of register TPC should be left at the default value.
M8 and N[9:8] (bits 4-2) of register TPC contain the MSB values for the TV PLL divider ratio’s. These controls are
described in detail in the PLLM (address 0Ah) and PLLN (address 0Bh) register descriptions.
MEM[0] (bit 5) of register TPC controls the input latch bias current level. The default value is recommended.
MEM[2:1] (bits 7-6) of register TPC control the memory sense amp reference level. The default value is recommended.
201-0000-048
DEFAULT:
SYMBOL:
Table 24: PLLCAP setting vs. Display Mode
TYPE:
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
BIT:
MEM2
R/W
PLLCAP
Value
Rev. 2.4,
7
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
1
MEM1
R/W
12/18/2006
6
0
Mode
MEM0
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
R/W
5
0
PLLCAP
Value
R/W
N9
4
0
1
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
R/W
N8
3
0
Symbol:
Address:
Bits:
R/W
M8
2
0
PLLCPI
R/W
TPC
09h
8
1
0
CH7019B
PLLCAP
R/W
0
0
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