UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 22

• Manufacturer Part Number: UPD16488AP
• Description: 1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
• Manufacturer: NEC [NEC]

5.3
is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and
reverse display is achieved by inverting the display level value.
address register (R13), and the blink data memory access register (R16).
the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display.
memory access register (R20) are used to select the reverse display area.
display will start and end. Next, the inverted X address register (R17) and the inverted data memory access register (R20)
are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with
each input of blink/reverse display data.
display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The
blink/reverse data (data bits D
point the blinking and/or reverse display of data begins. Figure 5-6 illustrates the relationship between the start line address,
end line address, blink/reverse data, and LCD display.
The µ PD16488A enables blinking display and reverse display in designated parts of the full dot display. A blinking display
The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X
First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next,
The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and the inverted data
First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse
The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking
After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which
22
Data
D3
D2
D1
D0
Blink/Reverse Display Circuit
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
00H
Figure 5-5. Correspondence Between Blink/Reverse Data and Segments
0
0
0
0
0
to D
7
Table 5-3. Inversion Manipulation and Display
sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 5-5.
Original Level
Four-level gray scale display mode
0, 0
0, 1
1, 0
1, 1
1
0
01H
Data Sheet S15745EJ2V0DS
0
0
0
1
B/W display mode
After Inversion
1, 1
1, 0
0, 1
0, 0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
0FH
1
1
1
1
µ µ µ µ PD16488A