UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 28
UPD16488AP
Manufacturer Part Number
UPD16488AP
Description
1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
Manufacturer
NEC [NEC]
Datasheet
1.UPD16488AP.pdf
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5.5
output pins.
there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed
asynchronously in relation to the LCD contents.
the frame AC drive method is generated for the LCD driver.
supplied from the master side.
The display clock generates timing signals for the line address circuit and the display data latch circuit.
Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver
Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently,
The internal common timing is generated from the display clock. As shown in Figure 5-10, a driver waveform based on
If a multiple set of PD16488A chips are used, the display timing signals (FR and FR
28
Display Timing Generator
Table 5-6. Relationship Between Operation Mode and FR, FR
Master (M/S
Operation Mode
Slave (M/S
Data Sheet S15745EJ2V0DS
L)
H)
Output
Input
FR
FR
Output
Input
SYNC
SYNC
SYNC
) for the slave side must be
PD16488A
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