kac-9630 ETC-unknow, kac-9630 Datasheet - Page 12

• Manufacturer Part Number: kac-9630
• Description: Cmos Image Sensor 126 H X 98 V Ultra Sensitive Global Shutter 580 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
I
The serial bus interface consists of the sda (serial data) and the
sclk (serial clock). The KAC-9630 can operate only as a slave.
The sclk pin is an input only and clocks the serial interface data
sclk. It is synchronised to mclk. A clock must be running at the
mclk pin in order to communicate with the serial control port.
Note mclk must be at least 10X sclk.
It is possible to communicate with the sensor via this port when
in power down mode.
General Definitions
Start/Stop Conditions
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
logic 0 to logic 1 transition on the sda pin, while the sclk pin is at
logic 1, is interrupted as the stop condition as shown in figure
13.
Device Address
The serial bus Device Address of the KAC-9630 is set to
1000100.
Acknowledgment
The KAC-9630 will hold the value of the sda pin to a logic 0 dur-
ing the logic 1 state of the Acknowledge clock pulse on sclk as
shown in figure 14.
Acknowledge (instead of an Acknowledge) followed by Stop Condition or a repeated Start Condition.See figure 18.
www.kodak.com/go/imagers 585-722-4385
2
sda
sclk
C Compatible Serial Interface
sda
sclk
from master
sda
sclk
sda
from sensor
start condition
START
S
S
S
S
Figure 13: Start/Stop Conditions
Device
Address
MSB
1
MSB
1
2
2
W
S
A
7
Address
Device
7
Figure 17: Serial Bus Write Byte Operation
Figure 18: Serial Bus Read Byte Operation
stop condition
Register
Address
Figure 16: Serial Bus Byte Format
8
Clock pulse
P
for ACK
W
byte complete
8
9
from receiver
A
ack signal
ACK
ACK
ACK
A
9
Register
Address
12
clock line
held low
S
Data Valid
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can only occur
when the logic level on the sclk pin is “0” as shown in figure 15.
Byte Format
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge except for the last byte.
The most significant bit of the byte is should always be transmit-
ted first. See figure 16.
Write Operation
A write operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. After the
master receives an Acknowledge from the sensor it must trans-
mit 8 bit internal register address. The sensor will respond with a
second Acknowledge signaling the master to start transmitting
data bytes. Each byte successfully received will be acknowl-
edged by the sensor with an Acknowledge.
The write operation is completed when the master asserts a
Stop Condition or a repeated Start Condition. See figure 17.
Read Operation
A read operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. After the
master receives an Acknowledge from the sensor it must trans-
mit the internal Register Address byte. The sensor will respond
with a second Acknowledge. The master must then issue a
repeated Start Condition followed by the sensor’s Device
Address and read bit. The sensor will respond with an Acknowl-
edge followed by the first Read Data byte. Each read data byte
must be acknowledged by the master.
The read operation is finished when the master asserts a Not
sda
sclk
Address
A
Device
1
Data
Byte
data valid
data line
stable;
Figure 14: Acknowledge
2
Figure 15: Data Validity
R
A
P
A
change
of data
allowed
8
Data
Byte
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ACK
bold sensor action
9
data valid
data line
from receiver
bold sensor action
stable;
ack signal
_
A
P
P