kac-9630 ETC-unknow, kac-9630 Datasheet - Page 14

• Manufacturer Part Number: kac-9630
• Description: Cmos Image Sensor 126 H X 98 V Ultra Sensitive Global Shutter 580 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Serial Digital Image Data Port
The sensor can be programmed so that the captured image is
placed onto a 4 bit serial digital image data port as shown in fig-
ure 24. The serial digital image data port consists of a single
data out pin (d[0]) and three synchronisation signals (d[1], hsync
& vsync).
When the sensor is programmed to work in this mode, all
optical and analog specifications will not be guaranteed.
Pins d[2:7] will be tri-stated.
The following sections provide a detailed description of the tim-
ing of the serial digital image data port.
Digital image data Data Out (d[0])
Pixel data is output on a single digital image data pin, d[0] and is
synchronized to the positive edge of mclk. The MSB of every
pixel byte will be transmitted first.
Synchronisation Signals
The integrated timing and control block controls the flow of data
onto the 8-bit digital port, three synchronisation outputs are pro-
vided:
www.kodak.com/go/imagers 585-722-4385
mclk
vsync
hsync
d[0]
mclk
vsync
hsync
d[0]
d[1]
d[1]
d[1]
hsync
vsync
8 Bit A/D
Figure 24: Serial Digital Image Data Port
b7
b7
b6
b6
is the bit synchronisation signal and will go high
for one clock cycle indicating the first bit (MSB)
of every pixel.
is the horizontal synchronisation output signal.
is the vertical synchronisation output signal in
video mode and the external frame trigger input
in snapshot mode.
C0
C0
b5
b5
row 100
row 100
C127
C127
b2
Figure 26: Serial Digital Image Data Port Timing Diagram In Video Mode
b2
b1
b1
Figure 27: Serial Digital Image Data Port Timing in Snapshot Mode
Digital
Video
b0
b0
horizontal
horizontal
Port
blanking
blanking
b7
b7
b6
b6
C0
C0
b5
b5
row 101
row 101
end of frame n
end of frame n
d[0]
d[1]
hsync
vsync
C127
C100
b2
b2
b1
b1
b0
b0
start of frame n+1
start of frame n+1
Idle + Integration
Idle Time
14
Time
Bit Synchronisation Output Pin (d[1]
The bit synchronisation output pin, d[1], is used as an indicator
for pixel data.
The d[1] output is synchronized to the positive edge of mclk and
will go high at the start of each pixel byte and remain high for
one mclk clock cycle as shown in figure 25.
Horizontal Synchronisation Output Pin (hsync)
The horizontal synchronisation output pin, hsync, is used as an
indicator for row data.
The hsync output pin is synchronized to the positive edge of
mclk and will go high at the start of each row and remain at that
level until the last pixel of that row is read out on d[0] as shown
in figure 20.
Vertical Synchronisation Pin in Video Mode (vsync)
The vertical synchronisation pin, vsync, in video mode is an out-
put and is used as an indicator for pixel data within a frame.
The vsync pin is synchronized to the positive edge of mclk and
will go high at the start of each frame and remain at that level
until the last pixel of that row in the frame is placed on d[0] as
shown in figure 21.
Vertical Synchronisation Pin in Snapshot Mode (vsync)
The vertical synchronisation pin, vsync, in snapshot mode is an
input and is used as an external trigger to start the capture of a
single frame.
The vsync pin must be forced high for at least two “mclk” cycles
during the idle state of the sensor to trigger a single frame as
shown in figure 23. The sensor can only be externally triggered
when it is in the idle state.
mclk
d[0]
d[1]
Integration
horizontal
Time horizontal
blanking
bit7 bit6 bit5 bit4 bit3 bit2
blanking
b7
Figure 25: d[1] timing diagram
b6
(Black Pixels)
C0
b5
row 1
b7
b6
C0
b5
(Black Pixels)
pixel 1
C127
row 1
b2
b1
C127
b0
horizontal
blanking
b2
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b1
b0
bit1 bit0 bit7 bit6
horizontal
blanking
b7
b6
C0
b5
row 2
b7
b6
C0
b5
row 2
b2
b1
b0