UPD72042BGT NEC [NEC], UPD72042BGT Datasheet - Page 41

• Manufacturer Part Number: UPD72042BGT
• Description: LSI DEVICE FOR Inter Equipment Bus (IEBus) PROTOCOL CONTROL
• Manufacturer: NEC [NEC]

[CEX]
The CEX flag is set and reset as described below.
[RAW]
output on the IRQ pin, and the IRQ flag of the FLG register is set. At this time. The microcomputer must reset the
[STM]
[IRQ]
flag changes from 0 to 1 (crash). When the FLG register is read with the IRQ flag set to 1, the IRQ flag is reset.
PD72042B by driving the RESET pin of the PD72042B low or by setting the SRST flag of the CTR register to 1.
1 : A command is currently being executed.
0 : Execution of a command has terminated. A command code can be set in CMR.
• Set
• Reset : When PD72042B command processing is terminated
1 : The PD72042B is running away.
0 : The PD72042B is not running away.
The RAW flag is used to indicate a microprogram crash in the PD72042B, as detected by a watchdog timer.
When the RAW flag is set to 1, a request to interrupt the microcomputer is issued. An interrupt pulse signal is
1 : Standby mode is set.
0 : Standby mode is not set.
1 : An interrupt request was made.
0 : No interrupt request is made.
The IRQ flag is set when a return code including the code in the RCR register is changed
For details of the return codes, see the description of the RCR register.
Note IRQ flag setting depends on the IRS value of the CMR register.
: When a command code is set in CMR
Data Sheet S13990EJ3V0DS
Note
, or when the RAW
PD72042B
41