CY28317ZC-2T SPECTRALINEAR [SpectraLinear Inc], CY28317ZC-2T Datasheet - Page 6

• Manufacturer Part Number: CY28317ZC-2T
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 25, 2006
CY28317-2 Serial Configuration Map
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Byte 3: Control Register 3
1. The serial bits will be read by the clock driver in the following
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Bit
Bit
Bit
Bit
44, 43
Pin#
Pin#
Pin#
39
10
17
16
15
14
13
11
10
11
26
27
48
47
Pin#
–
–
–
–
–
–
–
–
2
–
–
SDRAM6
PCI0_F
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Spread Select1
SEL2
SEL1
SEL0
FS_Override
SEL4
SEL3
Spread Select0
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
CPU0
CPU1
CPUT, CPUC
Reserved
SEL_48MHz
Name
Name
Name
Name
Default
Default
Default
1
0
Default
2. All unused register bits (reserved and N/A) should be
3. All register bits labeled “Write with 1" must be written to one
0
0
0
0
0
0
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
written to a “0” level.
during initialization.
Reserved
0 = 24 MHz
1 = 48 MHz
See definition in Bit[0]
See Table 6
See Table 6
See Table 6
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
See Table 6
See Table 6
‘00’ = OFF
‘01’ = –0.5%
‘10’ = ±0.5%
‘11’ = ±0.25%
Latched FS[4:0] inputs. These bits are read-only.
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Description
Description
Description
CY28317-2
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