CY28410OC SPECTRALINEAR [SpectraLinear Inc], CY28410OC Datasheet - Page 8

• Manufacturer Part Number: CY28410OC
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 21, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tance loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Cs1
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Ce1
X1
Ci1
Clock Chip
XTAL
Ci2
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
X2
Ce2
CLe
Cs2
Total Capacitance (as seen by the crystal)
=
3 to 6p
(
33pF
Pin
Trim
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
2.8pF
Trace
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28410
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