CY28412OC SPECTRALINEAR [SpectraLinear Inc], CY28412OC Datasheet - Page 10

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CY28412OC

Manufacturer Part Number
CY28412OC
Description
Manufacturer
SPECTRALINEAR [SpectraLinear Inc]
Datasheet
Rev 1.0, November 20, 2006
Below is an example showing the relationship of clocks
coming up.
FS_A, FS_B,FS_C
VDD Clock Gen
VTT_PW RGD#
PW RGD_VRM
Clock Outputs
Clock State
Clock VCO
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33MHz
USB, 48MHz
VDD _A = 2.0V
DOT96C
DOT96T
P ow er O ff
REF
State 0
Off
Off
PD
S0
Figure 4. Power-down Deassertion Timing Waveform
Figure 6. Clock Generator Power-up/Run State Diagram
0.2-0.3mS
State 1
Delay
Figure 5. VTT_PWRGD# Timing Diagram
VD D_A = off
<300 S, >200mV
Tdrive_PWRDN#
>0.25m S
VTT_PW RGD#
Tstable
<1.8ms
D elay
S1
W ait for
On
VTT_PW RG D # = toggle
VTT_PW R G D# = Low
O peration
N orm al
Sample Sels
S3
State 2
Inputs straps
On
S am ple
State 3
Enable O utputs
S2
W ait for <1.8m s
VTT_PW RGD# is ignored
Device is not affected,
CY28412
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