CY28510OC SPECTRALINEAR [SpectraLinear Inc], CY28510OC Datasheet - Page 3

• Manufacturer Part Number: CY28510OC
• Description: Peripheral I/O Clock Generator
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, yet the interface is
available at any time except power-down.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
20:27
29:36
38:45
11:18
2:8
Bit
10
19
28
37
46
....
....
....
....
(6:0)
1
9
Bit
7
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte count from master – 8 bits
Acknowledge from slave
Data byte 0 from master– 8 bits
Acknowledge from slave
Data byte 1 from master – 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N – 8 bits
Acknowledge from slave
Stop
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should
be '0000000'
Block Write Protocol
Description
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1. The Block Write and Block Read
protocol is outlined in Table 2, while Table 3 outlines the corre-
sponding byte write and byte read protocol.
The slave receiver address can be D0, D2, D4, or D6
depending on the state of the ADDSEL(0:1) pins.
Description
11:18
21:27
30:37
39:46
48:55
Bit
2:8
10
19
20
28
29
38
47
56
....
....
....
....
1
9
Repeat start
Read = 1
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Slave address – 7 bits
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte 0 from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data bytes from slave/acknowledge
Data byte N from slave – 8 bits
Not acknowledge
Stop
Block Read Protocol
Description
CY28510
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