CS43L41-KZ CIRRUS [Cirrus Logic], CS43L41-KZ Datasheet - Page 11

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CS43L41-KZ

Manufacturer Part Number
CS43L41-KZ
Description
Low Power 24-Bit, 96 kHz DAC with Volume Control?
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet

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SWITCHING CHARACTERISTICS - CONTROL PORT
(T
Notes: 12. t
DS473PP1
SPI
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
A
= 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, C
®
Mode
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
spi
only needed before first falling edge of CS after RST rising edge. t
SCK
< 1 MHz
CCLK
CDIN
RST
CS
Parameter
t srs
t spi
t r2
Figure 5. SPI Control Port Timing
t css
(Note 12)
(Note 13)
(Note 14)
(Note 14)
t scl
t f2
t dsu t
t sch
dh
Symbol
f
t
t
t
t
t
t
t
t
sclk
dsu
csh
sch
t
t
css
srs
spi
scl
dh
r2
f2
L
= 30 pF)
Min
500
500
1.0
20
66
66
40
15
-
-
-
spi
t csh
= 0 at all other times.
Max
100
100
6
-
-
-
-
-
-
-
-
CS43L41
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
11

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