CS43L41-KZ CIRRUS [Cirrus Logic], CS43L41-KZ Datasheet - Page 31

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CS43L41-KZ

Manufacturer Part Number
CS43L41-KZ
Description
Low Power 24-Bit, 96 kHz DAC with Volume Control?
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet

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Part Number:
CS43L41-KZ
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DS473PP1
SDATA
SDATA
SDATA
Right Justified, 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 20-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 16-Bit DataINT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
LRCK
LRCK
SCLK
LRCK
SCLK
SCLK
1 0
0
19 18
Internal SCLK Mode
Internal SCLK Mode
Internal SCLK Mode
17 16
23 22 21 20 19 18
15 14 13 12 11 10
15 14 13 12 11 10
32 clocks
32 clocks
Left Channel
Left Channel
Left Channel
32 clocks
9 8 7
9 8 7
Figure 23. CS43L41 Format 3
Figure 24. CS43L41 Format 4
Figure 25. CS43L41 Format 5
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
6 5 4 3 2 1 0
Right Justified, 24-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 48 Cycles per LRCK
Period
Right Justified, 20-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 40 Cycles per LRCK
Period
Right Justified, 16-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 32 Cycles per LRCK
Period
19 18
17 16
23 22 21 20 19 18
15 14 13 12 11 10
External SCLK Mode
External SCLK Mode
External SCLK Mode
15 14 13 12 11 10
Right Channel
Right Channel
Right Channel
9 8 7
9 8 7
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
6 5 4 3 2 1 0
CS43L41
31

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