CS43L41-KZ CIRRUS [Cirrus Logic], CS43L41-KZ Datasheet - Page 15

• Manufacturer Part Number: CS43L41-KZ
• Description: Low Power 24-Bit, 96 kHz DAC with Volume Control?
• Manufacturer: CIRRUS [Cirrus Logic]

4.
4.1
4.2
DS473PP1
MCLKDIV
AMUTE
Reserved
AMUTE
0
1
0
1
REGISTER BIT DESCRIPTION
7
7
MASTER CLOCK DIVIDE ENABLE
AUTO-MUTE
MCLK Control Register (address 00h)
Access:
Default:
Function:
Mode Control Register (address 01h)
Access:
Default:
Function:
Disabled
Enabled
Disabled
Enabled
R/W in I
0 - Disabled
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
Note: This feature is present on revision C and newer devices. For backward compatibility with pre-
vious revision devices, this bit defaults to zero.
R/W in I
1 - Enabled
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and mut-
ing is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period. The muting function is effected, similar to
volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
Table 1. Master Clock Divide Enable
Reserved
DIF2
6
6
Table 2. Auto-Mute Enable
2
2
C and write only in SPI.
C and write only in SPI.
Reserved
DIF1
5
5
MODE
MODE
Reserved
DIF0
4
4
Reserved
DEM1
3
3
Reserved
DEM0
2
2
MCLKDIV
POR
1
1
CS43L41
Reserved
PDN
0
0
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