AM186ED AMD [Advanced Micro Devices], AM186ED Datasheet
AM186ED
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AM186ED Summary of contents
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... DISTINCTIVE CHARACTERISTICS TM E86 family 80C186- and 80C188-compatible microcontroller with enhanced bus interface – Lower system cost with higher performance – 3.3-V ± 0.3-V operation (Am186EDLV microcontrollers) Programmable DRAM Controller – Supports zero-wait-state operation with 50-ns DRAM at 40 MHz, 60- MHz, 70- MHz – Includes programmable CAS-before-RAS ...
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... Am186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM INT3/INTA1/IRQ CLKOUTA INT6–INT4** CLKOUTB X2 X1 Clock and V CC Power Interrupt GND Management Control Unit Unit Watchdog Timer (WDT) Control Control Registers Registers RES Control Refresh Registers Control ARDY Unit SRDY S2/BTSEL S1– ...
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... AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 1 KI\W Note: The industrial version of the Am186ED as well as the Am186EDLV are available in 20 and 25 VC\W or MHz operating frequencies only. KC\W The Am186ED and Am186EDLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies ...
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... Related Documents ....................................................................................................... 10 Third-Party Development Support Products .................................................................. 10 Customer Service .......................................................................................................... 10 KEY FEATURES AND BENEFITS ............................................................................................ 10 Application Considerations .............................................................................................11 COMPARING THE AM186ED/EDLV TO THE AM186ES/ESLV MICROCONTROLLERS ........ 12 Integrated DRAM Controller ........................................................................................... 12 Enhanced Refresh Control Unit ..................................................................................... 13 Option to Overlap DRAM with PCS ............................................................................... 13 Additional Serial Port Mode for DMA Support of 9-bit Protocols .................................... 13 Option to Boot from 8- or 16-bit Memory ...
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... Memory Organization ..................................................................................................... 33 I/O Space ....................................................................................................................... 33 BUS OPERATION ..................................................................................................................... 34 BUS INTERFACE UNIT ............................................................................................................. 36 Nonmultiplexed Address Bus ......................................................................................... 36 DRAM Address Multiplexing .......................................................................................... 36 Programmable Bus Sizing ............................................................................................. 37 Byte-Write Enables ........................................................................................................ 37 Data Strobe Bus Interface Option .................................................................................. 37 DRAM INTERFACE ................................................................................................................... 37 PERIPHERAL CONTROL BLOCK ............................................................................................ 38 Reading and Writing the PCB ........................................................................................ Am186ED/EDLV Microcontrollers 5 ...
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... Read Cycle (33 MHz and 40 MHz) ................................................................................ 65 READ CYCLE WAVEFORMS ................................................................................................... 66 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 67 Write Cycle (20 MHz and 25 MHz) ................................................................................ 67 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 68 Write Cycle (33 MHz and 40 MHz) ................................................................................ 68 WRITE CYCLE WAVEFORMS .................................................................................................. Am186ED/EDLV Microcontrollers ...
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... SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................ 84 Reset and Bus Hold (33 MHz and 40 MHz) ................................................................... 84 RESET AND BUS HOLD WAVEFORMS ................................................................................... 85 Reset Waveforms .......................................................................................................... 85 Signals Related to Reset Waveforms ............................................................................ 85 Bus Hold Waveforms—Entering .................................................................................... 86 Bus Hold Waveforms—Leaving ..................................................................................... 86 TQFP PHYSICAL DIMENSIONS ............................................................................................... 87 PQFP PHYSICAL DIMENSIONS .............................................................................................. Am186ED/EDLV Microcontrollers 7 ...
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... Programming the Bus Width of Am186ED/EDLV Microcontrollers ........................ 37 Table 8 Peripheral Control Block Register Map .................................................................. 39 Table 9 Am186ED/EDLV Microcontrollers Maximum DMA Transfer Rates ....................... 46 Table 10 Typical Power Consumption Calculation for the Am186EDLV Microcontroller ...... 50 Table 11 Thermal Characteristics ( C/Watt) ......................................................................... 51 Table 12 Typical Power Consumption Calculation ............................................................... 52 Table 13 Junction Temperature Calculation ......................................................................... 52 Table 14 Typical Ambient Temperatures (° ...
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... Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16- bit external data bus Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte ...
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... The Am186ED/EDLV microcon- trollers are a higher-performance, highly integrated version of the 80C186/188 microprocessors, offering an attractive migration path. In addition, the Am186ED/ EDLV microcontrollers offer application-specific fea- tures that can enhance the system functionality of the Am186ES/ESLV and Am188ES/ESLV microcontrol- lers ...
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... Clock Generation The integrated clock generation circuitry of the Am186ED/EDLV microcontrollers enables the use crystal frequency. The Am186ED design in Figure 1 achieves 40-MHz CPU operation, while using a 40- MHz crystal. Figure 1. Am186ED Microcontroller Example Direct Memory Interface Example Figure 1 illustrates the direct memory interface of the Am186ED microcontroller. The processor’ ...
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... Am186ED/EDLV microcontrollers and no external logic is r equired. The DRAM multiplexed address pins are connected to the odd address pins starting with A1 on the Am186ED/EDLV microcontrollers to MA0 on the DRAM. The correct row and column addresses are generated on these pins during a DRAM access. The UCAS and LCAS are used to select which byte of the DRAM is accessed during a read or write ...
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... USIZ, LSIZ, MSIZ, and IOSIZ bits in the AUXCON register. Improved External Bus Master Support When the bus is arbitrated away from the Am186ED/ EDLV microcontrollers using the HOLD pin, the chip selects are driven High (negated) and then held High with an internal ~10-kohm pullup ...
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... AD14 16 AD7 17 AD15 18 19 S6/CLKDIV2 20 UZI TXD1 21 RXD1 22 23 CTS0/ENRX0 RXD0 24 TXD0 25 Note: Pin 1 is marked for orientation Am186ED/EDLV Microcontrollers Am186ED/EDLV Microcontrollers 75 INT4 MCS1/UCAS 74 73 MCS0 72 DEN/DS 71 DT/R 70 NMI 69 SRDY 68 HOLD 67 HLDA 66 WLB 65 WHB 64 GND ...
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... TQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers Sorted by Pin Number Pin No. Name Pin No. 1 AD0 2 AD8 3 AD1 4 AD9 5 AD2 6 AD10 7 AD3 8 AD11 9 AD4 10 AD12 11 AD5 12 GND 13 AD13 14 AD6 AD14 17 AD7 18 AD15 19 S6/CLKDIV2/PIO29 20 UZI/PIO26 21 TXD1/PIO27 22 RXD1/PIO28 23 CTS0/ENRX0/PIO21 24 RXD0/PIO23 25 TXD0/PIO22 Name Pin No ...
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... TQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers Sorted by Pin Name Pin Name No. Pin Name A0 63 AD5 A1 62 AD6 A2 60 AD7 A3 59 AD8 A4 58 AD9 A5 57 AD10 A6 56 AD11 A7 55 AD12 A8 54 AD13 A9 53 AD14 A10 52 AD15 A11 51 ALE A12 50 ARDY A13 49 BHE/ADEN A14 ...
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... GND 19 A19 20 A18 A17 23 A16 24 A15 25 A14 26 A13 27 A12 28 A11 29 A10 30 A9 Note: Pin 1 is marked for orientation Am186ED/EDLV Microcontrollers 80 AD1 79 AD8 78 AD0 77 DRQ0/INT5 76 DRQ1/INT6 75 TMRIN0 74 TMROUT0 73 TMROUT1 72 TMRIN1 71 RES 70 GND 69 MCS3/RAS1 68 MCS2/LCAS ...
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... PQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers Sorted by Pin Number Pin No. Name Pin No. 1 RXD0/PIO23 26 2 TXD0/PIO22 27 RTS0/RTR0 PIO20 4 BHE/ADEN ALE 32 8 ARDY 33 9 S2/BTSEL GND CLKOUTA 41 17 ...
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... PQFP PIN DESIGNATIONS—Am186ED/EDLV Microcontrollers Sorted by Pin Name Pin Name No. Pin Name A0 40 AD5 A1 39 AD6 A2 37 AD7 A3 36 AD8 A4 35 AD9 A5 34 AD10 A6 33 AD11 A7 32 AD12 A8 31 AD13 A9 30 AD14 A10 29 AD15 A11 28 ALE A12 27 ARDY A13 26 BHE/ADEN A14 ...
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... LOGIC SYMBOL—Am186ED/EDLV MICROCONTROLLERS X1 X2 Clocks CLKOUTA CLKOUTB 20 A19–A0 * Address and 16 AD15–AD0 Address/Data Buses S6/CLKDIV2 * * UZI ALE S2/BTSEL 2 S1–S0 HOLD HLDA RD WR Bus Control DT/R * DEN/DS * ARDY SRDY * BHE/ADEN WHB WLB TMRIN0 * * TMROUT0 Timer Control TMRIN1 * * TMROUT1 32 shared Programmable I/O Control PIO32– ...
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... During a bus hold or reset condition, the address bus high-impedance state. While the Am186ED/EDLV microcontrollers are directly connected to DRAM, A19–A0 will serve as the nonmultiplexed address bus for SRAM, FLASH, PROM, EPROM, and peripherals. The odd address ...
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... ENRX0—This pin provides the Enable Receiver Request for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial Am186ED/EDLV Microcontrollers . There is a weak internal 1 –t bus cycle, regardless of the ...
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... This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186ED/EDLV microcontrollers’ HOLD latency time, that is, the time between HOLD request and HOLD acknowledge function of the activity occur- ring in the processor when the HOLD request is re- ceived ...
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... IRQ—When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller. Am186ED/EDLV Microcontrollers ...
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... MCS2/LCAS/PIO24 Midrange Memory Chip Select (output, synchronous, internal pullup) Lower Column Address Strobe This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of Am186ED/EDLV Microcontrollers 25 ...
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... Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range Am186ED/EDLV Microcontrollers ...
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... I/O or memory address space). The base address of the peripheral memory block is programmable. The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM Am186ED/EDLV Microcontrollers 27 ...
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... During a bus hold condition, A2 retains its previously latched value. PIO31–PIO0 (Shared) Programmable I/O Pins (input/output, asynchronous, open-drain) The Am186ED/EDLV microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown ...
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... PCS1 PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 PCS5/A1 PCS6/A2 RTS0/RTR0 RXD0 RXD1 (1,2) S6/CLKDIV2 SRDY TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD0 TXD1 (1,2) UZI Am186ED/EDLV Microcontrollers PIO No Power-On Reset Status (3) 7 Normal operation (3) 8 Normal operation (3) 9 Normal operation 21 Input with pullup (3) 5 Normal operation 12 Input with pullup 13 ...
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... I/O indicator. S2–S0 float during bus hold and hold acknowledge conditions. The S2–S0 pins are encoded as shown in Table 4. BTSEL—The Am186ED/EDLV microcontrollers can boot from 8- or 16-bit wide nonvolatile memory, based on the state of the BTSEL pin. If BTSEL is pulled High or left floating, an internal pullup sets the boot mode option to 16-bit ...
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... This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. Am186ED/EDLV Microcontrollers 31 ...
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... This pin and the X1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin Am186ED/EDLV Microcontrollers ...
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... The Am186ED/ EDLV microcontrollers are backward-compatible with the 80C186 and 80C188 microcontrollers. A full description of all the Am186ED/EDLV microcon- troller registers and instructions is included in the Am186ED/EDLV Microcontrollers User’s Manual , or- der# 21335A. ...
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... The industry-standard 80C186 and 80C188 microcon- trollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t clock phase. The Am186ED/EDLV microcontrollers 1 continue to provide the multiplexed AD bus and, in ad- dition, provides a nonmultiplexed address (A) bus. The A bus provides an address to the system for the com- plete bus cycle (t – ...
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... Address Phase CLKOUTA A19–A0 AD7–AD0 Address (Read) AD15–AD8 (Read or Write) AD7–AD0 Address (Write) LCS or UCS or MCSx, PCSx Figure 6. 8-Bit Mode—Normal Read and Write Operation Am186ED/EDLV Microcontrollers Data Phase Address Data Data Data ...
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... Data strobe bus interface option The standard 80C186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. On the Am186ED/EDLV microcontrollers, new byte write enables, DRAM con- trol logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. ...
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... A chip select signal, ARDY, DS, and other control sig- nals (RD/WR) can control the interface of 68K-type ex- ternal peripherals to the AD bus. DRAM INTERFACE The Am186ED/EDLV microcontrollers support up to two banks of DRAM. The use of DRAM can signifi- cantly reduce the memory costs for applications using more than 64K of RAM. No performance is lost except for the slight overhead of periodically refreshing the DRAM ...
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... For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner runs correctly on the Am186ED/EDLV mi- crocontrollers with the PCB overlayed on either 8- or 16-bit address spaces. Unaligned reads and writes to the PCB result in unpre- dictable behavior ...
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... The register has been modified from the Am186ES/ 74h Am188ES microcontrollers. 72h 2. The previous Memory Partition Register (MDRAM) 70h has been removed and its functionality replaced with the CAS-before-RAS refresh mode. 66h Am186ED/EDLV Microcontrollers Offset 62h 60h 5Eh 5Ch 5Ah 58h 56h ...
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... Phase-Locked Loop In a traditional 80C186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. Because of the PLL on the Am186ED/EDLV mi- crocontrollers, the internal clock generated by the Am186ED/EDLV microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crys- tal inputs (X1 and X2) and generates a 45– ...
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... Individual drive enable bits allow selective enabling of just one or both of these clock outputs. Power-Save Operation The power-save mode of the Am186ED/EDLV micro- controllers reduces power consumption and heat dissi- pation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock fre- quency ...
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... The ARDY signal on the Am186ED/EDLV microcon- trollers is a true asynchronous ready signal. The ARDY pin accepts a rising edge that is asynchronous to CLK- OUTA and is active High. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an addi- tional clock period may be added ...
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... UCS can be changed in the AUXCON register. If UCS boots as a 16-bit space not re-configurable to 8-bit. This allows for cheaper 8- bit-wide memory to be used for booting the Am186ED/ EDLV microcontrollers, while speed-critical code and data can be executed from 16-bit-wide lower memory. ...
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... DRQ0 and DRQ1. These two in- terrupts are available if the associated DMA is not en- abled or is being used with internal synchronization. The Am186ED/EDLV microcontrollers provide up to six interrupt sources not present on the 80C186 and 80C188 microcontrollers. There are up to three addi- tional external interrupt pins— ...
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... PULSE WIDTH DEMODULATION For many applications, such as bar-code reading necessary to measure the width of a signal in both its High and Low phases. The Am186ED/EDLV microcon- trollers provide a pulse-width demodulation (PWD) op- tion to fulfill this need. The PWD bit in the System Configuration Register (SYSCON) enables the PWD option ...
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... The DMA control registers define the channel operation. All registers can be modified dur- ing any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation. Table 9. Am186ED/EDLV Microcontrollers Maximum DMA Transfer Rates Type of Synchronization Selected ...
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... DMA activity to halt. This allows the CPU to respond quickly to the NMI request. ASYNCHRONOUS SERIAL PORTS The Am186ED/EDLV microcontrollers provide two in- dependent asynchronous serial ports. These ports pro- vide full-duplex, bidirectional data transfer using several industry-standard communications protocols. ...
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... PROGRAMMABLE I/O (PIO) PINS There are 32 pins on the Am186ED/EDLV microcon- trollers that are available as user-programmable I/O signals. Table 2 on page 29 and Table 3 on page 29 list the PIO pins. Each of these pins can be used as a user- programmable input or output signal if the normal shared function is not needed ...
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... V cc Am186EDLV Microcontroller +0 Commercial ( MHz................................. 3.3 V ± 0 Where case temperature ambient temperature A *Industrial versions of Am186ED microcontrollers are available in 20 and 25 MHz operating frequencies only. Test Conditions I = 2.5 mA (S2–S0 2.0 mA (others 1.5 mA (S2–S0 1.0 mA (others –2 2.4 V ...
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... I (mA Figure 11. Typical I Am186EDLV Microcontroller 33 MHz 25 MHz 20 MHz Clock Frequency (MHz) Versus Frequency for Am186ED Microcontroller cc Am186ED/EDLV Microcontrollers Preliminary Min Max Unit 10 20 Volts / 1000 = P Typical Power CC in Watts Typical I Volts CC 4.0 3.6 0.288 4.0 3.6 0.360 ...
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... THERMAL CHARACTERISTICS TQFP Package The Am186ED microcontroller is specified for operation with case temperature ranges from +100 C for a commercial device. Case temperature is measured at the top center of the package as shown in Figure 13. The various temperatures and thermal resistances can be determined using the equations in Figure 14 with information given in Table 11 ...
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... Typical Ambient Temperatures The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186ED microcontroller is a case temperature T degrees Centigrade measured at the top center C of the package. An increase in the ambient temperature causes a proportional increase Microcontrollers MHz are specified as 5 ...
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... MHz 0 fpm Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board Linear Feet per Minute Airflow 0 fpm 200 fpm 55.2 62.2 63.0 68.8 72.0 76.4 77.6 81.1 200 fpm 400 fpm Airflow (Linear Feet Per Minute) Am186ED/EDLV Microcontrollers 400 fpm 600 fpm 67.0 69.3 72.7 74.7 79.4 80.8 83.5 84.7 600 fpm 53 ...
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... Figure 16. Typical Ambient Temperatures for TQFP with a 2-Layer Board Linear Feet per Minute Airflow 0 fpm 200 fpm 45.7 57.5 55.2 65.0 66.1 73.5 72.9 78.8 200 fpm 400 fpm Airflow (Linear Feet Per Minute) Am186ED/EDLV Microcontrollers 400 fpm 600 fpm 64.6 67.0 70.8 72.7 77.9 79.4 82.3 83.5 600 fpm ...
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... Figure 17. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board Linear Feet per Minute Airflow 0 fpm 200 fpm 78.8 81.1 82.5 84.4 86.7 88.2 89.4 90.6 200 fpm 400 fpm Airflow (Linear Feet Per Minute) Am186ED/EDLV Microcontrollers 400 fpm 600 fpm 83.5 85.8 86.4 88.3 89.7 91.2 91.7 92.9 600 fpm 55 ...
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... Figure 18. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board Linear Feet per Minute Airflow 0 fpm 200 fpm 71.7 74.0 76.6 78.6 82.3 83.8 85.8 87.0 200 fpm Airflow (Linear Feet Per Minute) Am186ED/EDLV Microcontrollers 400 fpm 600 fpm 76.4 78.8 80.5 82.5 85.3 86.7 88.2 89.4 600 fpm 400 fpm ...
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... Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance Off State Invalid Invalid Am186ED/EDLV Microcontrollers ) state i 57 ...
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... X1 to CLKOUTA Skew X1 to CLKOUTB Skew CLKOUTA High to RAS Inactive X1 Fall Time X1 Period X1 Rise Time CLKOUTA Fall Time ARDY Active Hold Time AD Address Valid Delay and BHE Address Hold AD Address Float Delay CLKOUTA Low Time X1 Low Time CLKOUTA Period Am186ED/EDLV Microcontrollers ...
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... RAS To Column Address Delay Time with 0 Wait States RAS to Column Address Delay Time with 1 or More Wait States 57 RES Setup Time 29 RD Inactive to AD Address Active 59 RD High to Data Hold on AD Bus 94 RD High to Data Bus Turn-off Time 28 RD Inactive to ALE High Am186ED/EDLV Microcontrollers Description 59 ...
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... Description RD Pulse Width RAS Inactive Pulse Width (0 Wait States) RAS Inactive Pulse Width (1 Wait State) SRDY Transition Setup Time WR Inactive to DEN Inactive Data Hold after WR WR Inactive to ALE High WR Pulse Width Am186ED/EDLV Microcontrollers ...
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... RD Inactive to ALE High RD Inactive to AD Address Active Data Hold Time Control Inactive Delay WR Pulse Width WR Inactive to ALE High Data Hold after WR WR Inactive to DEN Inactive X1 Period X1 Low Time X1 High Time X1 Fall Time X1 Rise Time DS Inactive to ALE Inactive CLKOUTA Period Am186ED/EDLV Microcontrollers 61 ...
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... CLKOUTA High to A Address Valid X1 to CLKOUTA Skew X1 to CLKOUTB Skew CLKOUTA to CLKOUTB Skew A Address Valid to WHB, WLB Low Chip Select to ARDY Low ARDY Assert to Data Valid DS Low to Data Driven DS Low to Data Valid DS High to Data Invalid—Read DS High to Data Bus Turn-off Time Am186ED/EDLV Microcontrollers ...
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... CLKOUTA Low to CAS Inactive CLKOUTA High to RAS Active CLKOUTA Low to RAS Inactive RAS Inactive Pulse Width (0 Wait States) RAS Inactive Pulse Width (1 Wait State) RAS To Column Address Delay Time with 0 Wait States RAS to Column Address Delay Time with 1 or More Wait States Am186ED/EDLV Microcontrollers 63 ...
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... CLCL 0 (a) t –3 CLCH (a) t –10=40 CLCL t –2=21 CLCH ( –3 CLCL CHCL 0 0 =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max Unit ...
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... CLCL 0 (a) t –3 CLCH (a) t –10=20 CLCL t –2=11.5 CLCH ( –3 CLCL CHCL 0 0 =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 40 MHz Max Min Max Unit ...
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... MCS1–MCS0, PCS6–PCS5, PCS3–PCS0 DEN DT/R (c) 22 S2–S0 3 UZI Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b Am186ED/EDLV microcontrollers in 8-bit mode c Changes in t phase preceding next bus cycle if followed by read, INTA, or halt Address INVALID ...
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... CLCH (a) t –10=40 CLCL (a) t –3 CLCH t –2=21 CLCH t +t –3 CLCL CHCL –3 CHCL 35 =0.45 V and V 2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max Unit ...
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... CLCH (a) t –10=20 CLCL (a) t –3 CLCH t –2=11.5 CLCH t +t –3 CLCL CHCL –3 CHCL 20 =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 40 MHz Max Min Max Unit ...
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... MCS3–MCS0, PCS6–PCS5, PCS3–PCS0 DEN DS DT/R (c) 22 S2–S0 3 UZI Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b Am186ED/EDLV microcontrollers in 8-bit mode c Changes in t phase preceding next bus cycle if followed by read, INTA, or halt Address INVALID ...
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... 130 150 150 170 170 190 190 210 Am186ED/EDLV Microcontrollers Preliminary 33 MHz 40 MHz Max Min Max Min Max ...
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... Addr. 101 Column Row 110 102 104 Addr. 68 101 Row Column 110 102 104 25 Am186ED/EDLV Microcontrollers Data 2 103 108 105 Data 2 107 109 105 27 71 ...
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... Addr. Data 101 Row Column 110 102 104 Addr. 101 Row Column 110 102 104 20 Am186ED/EDLV Microcontrollers 103 108 105 Data 107 109 105 31 ...
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... CAS before RAS cycle timing is always 7 clocks, independent of wait state timing. b The RD output connects to the DRAM output enable (OE) pin for read operations FFFF 101 X X 106 104 25 Am186ED/EDLV Microcontrollers 107 109 105 27 73 ...
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... CLCL (a) t –2 CLCH t =0 CLAX ( =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max Unit –10=30 CLCL –2 CLCH ...
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... CLCL (a) t CLCH t =0 CLAX ( =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 40 MHz Max Min Max Unit –5=20 CLCL CLCH ...
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... If followed by a write cycle, this change occurs in the state preceding that write cycle Address 7 Invalid BHE 20 ( Status . 4 (min). Am186ED/EDLV Microcontrollers (b) 2 Ptr ( (d) ...
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... V and V =2.4 V, except at X1 where MHz Min –10=20 CLCL ( =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max Unit –10=30 ...
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... SOFTWARE HALT CYCLE WAVEFORMS CLKOUTA 68 A19–A0 5 S6, AD15–AD0 ALE 9 DEN 19 DT/R S2– Invalid Address Invalid Address Status Am186ED/EDLV Microcontrollers ...
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... MHz Min 50 (a) 15 (a) 15 (a) (a) 50 =50 pF) 0.5t –2=23 L CLCL =50 pF) 0.5t –2=23 L CLCL =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max 0.5t –2=18 CLCL 0.5t –2=18 CLCL ...
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... MHz Min 30 (a) 10 (a) 10 (a) (a) 30 =50 pF) 0.5t –1.5 =13.5 L CLCL =50 pF) 0.5t –1.5 =13.5 L CLCL =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 40 MHz Max Min Max 7.5 7 0.5t –1.25 =11.25 CLCL 0.5t –1.25 =11.25 CLCL ...
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... CLOCK WAVEFORMS Clock Waveforms—Active Mode CLKOUTA (Active, F=000) CLKOUTB Clock Waveforms—Power-Save Mode X2 X1 CLKOUTA (Power-Save, F=010) CLKOUTB (Like X1, CBF=1) CLKOUTB (Like CLKOUTA, CBF= Am186ED/EDLV Microcontrollers ...
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... V and V =2.4 V, except at X1 where MHz Description Min (a) 8 (a) 3 ( (a) 10 (b) 8 (b) 8 =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 25 MHz Max Min Max Unit – ...
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... Am186ED/EDLV Microcontrollers ...
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... This timing must be met to guarantee recognition at the next clock Description Min Description Min =0.45 V and V =2.4 V, except at X1 where Am186ED/EDLV Microcontrollers Preliminary 20 MHz 25 MHz Max Min Max ...
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... RESET and BUS HOLD WAVEFORMS Reset Waveforms X1 RES CLKOUTA Signals Related to Reset Waveforms RES S2/BTSEL, CLKOUTA BHE/ADEN, S6/CLKDIV2, and UZI AD15–AD0 Three-State Am186ED/EDLV Microcontrollers 57 Three-State 85 ...
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... Case 2 CLKOUTA HOLD HLDA AD15–AD0, DEN A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB Case Case Am186ED/EDLV Microcontrollers ...
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... TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack 100 1 1.35 1.45 0.17 0.27 1.00 REF. Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only 13.80 14.20 15.80 16.20 11 – 13 1.60 MAX 11 – 13 0.50 BSC Am186ED/EDLV Microcontrollers 15.80 16.20 13.80 14.20 16-038-PQT-2_AI PQL100 9.3. ...
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... Am186, Am188, E86, K86, Élan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies 17.00 17.40 13.90 14.10 Pin 50 0.65 BASIC Am186ED/EDLV Microcontrollers Pin 80 18.85 REF 19.90 20.10 23.00 23.40 3.35 MAX SEATING PLANE ...