AM186ED AMD [Advanced Micro Devices], AM186ED Datasheet - Page 67

• Manufacturer Part Number: AM186ED
• Description: High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Write Cycle (20 MHz and 25 MHz)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
General Timing Responses
Write Cycle Timing Responses
No.
10
12
13
14
16
17
18
19
20
21
22
23
99
30
31
32
33
34
35
41
65
67
68
87
98
11
3
4
5
6
7
8
9
L
Symbol
t
t
t
t
t
t
t
t
t
t
t
DSHDIW
t
t
t
WHDEX
t
CHCSX
t
CHCSV
t
t
t
t
t
CLCSV
CXCSX
t
CVCTV
CVDEX
CHCTV
CLDOX
CVCTX
DSHLH
t
t
=50 pF. For switching tests, V
t
t
t
t
t
t
t
t
t
WLWH
WHDX
CHDX
WHLH
CHSV
CLSH
CLDV
CHLH
AVCH
DXDL
AVWL
CHAV
CLAV
CLAX
CHLL
LHAV
AVBL
LHLL
AVLL
LLAX
PLAL
Status Active Delay
Status Inactive Delay
AD Address Valid Delay and BHE
Address Hold
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
AD Address Valid to ALE Low
AD Address Hold from ALE Inactive
AD Address Valid to Clock High
MCS/PCS Active Delay
MCS/PCS Hold from Command Inactive
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
Control Active Delay 1
DS Inactive Delay
Control Active Delay 2
ALE High to Address Valid
PCS Active to ALE Inactive
Data Hold Time
Control Inactive Delay
WR Pulse Width
WR Inactive to ALE High
Data Hold after WR
WR Inactive to DEN Inactive
DS Inactive to ALE Active
A Address Valid to WR Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to A Address Valid
A Address Valid to WHB, WLB Low
DS High to Data Invalid—Write
Parameter
Description
(a)
IL
=0.45 V and V
Am186ED/EDLV Microcontrollers
(b)
(b)
(a)
(a)
P R E L I M I N A R Y
(a)
(a)
(a)
IH =
(a)
2.4 V, except at X1 where V
t
2t
CLCL
t
t
CLCL
t
CLCL
CLCL
CLCH
t
t
t
t
t
t
CLCH
CHCL
CLCH
CLCH
CLCH
CHCL
+t
Min
–10=40
–10=40
20
15
35
–10=90
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–2=21
CHCL
20 MHz
–2
–2
–3
–3
–2
–2
–3
Max
Preliminary
25
25
25
25
15
25
25
25
25
15
25
25
28
25
25
25
25
IH
=V
t
2t
CLCL
t
t
CLCL
CLCL
t
CC
CLCL
CLCH
t
t
t
t
t
t
CLCH
CHCL
CLCH
CLCH
CLCH
CHCL
– 0.5 V.
+t
Min
–10=30
15
15
–10=30
30
–10=70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–2=16
CHCL
25 MHz
–2
–2
–2
–2
–3
–3
–3
Max
20
20
20
20
15
20
20
20
20
15
20
20
24
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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