AM186ED AMD [Advanced Micro Devices], AM186ED Datasheet - Page 64

• Manufacturer Part Number: AM186ED
• Description: High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Read Cycle (20 MHz and 25 MHz)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C
a Equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
c
64
General Timing Requirements
General Timing Responses
Read Cycle Timing Responses
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
99
24
25
26
27
28
29
41
59
66
67
68
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
1
2
3
4
5
6
8
9
L
Symbol
=50 pF. For switching tests, V
t
t
t
t
t
t
t
t
t
t
CXCSX
CHCSX
CVDEX
CHCTV
t
CHCSV
t
t
t
t
t
t
CLCSV
t
CVCTV
t
t
t
t
DSHLH
t
t
t
t
t
t
t
t
t
t
t
t
CHSV
CHDX
RHDX
DVCL
CLDX
CLSH
CLAX
CHLH
AVCH
DXDL
RLRH
CLRH
RHLH
RHAV
CHAV
CLAV
CHLL
LLAX
CLAZ
LHAV
PLAL
AZRL
CLRL
AVRL
LHLL
AVLL
Data in Setup
Data in Hold
Status Active Delay
Status Inactive Delay
AD Address Valid Delay and BHE
Address Hold
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
AD Address Valid to ALE Low
AD Address Hold from ALE Inactive
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
MCS/PCS Hold from Command Inactive
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
Control Active Delay 1
DEN Inactive Delay
Control Active Delay 2
ALE High to Address Valid
PCS Active to ALE Inactive
AD Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
RD Inactive to AD Address Active
DS Inactive to ALE Active
RD High to Data Hold on AD Bus
A Address Valid to RD Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to A Address Valid
Parameter
(c)
Description
IL
=0.45 V and V
Am186ED/EDLV Microcontrollers
(b)
(b)
(a)
P R E L I M I N A R Y
(a)
(a)
(a)
(c)
(a)
IH
(a)
(a)
=2.4 V, except at X1 where V
t
2t
CLCL
t
t
CLCL
CLCL
t
CLCL
CLCH
t
t
t
t
t
CLCH
CHCL
CLAX
CLCH
CLCH
+ t
Min
–10=40
–10=40
10
20
15
–15=85
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–2=21
CHCL
20 MHz
=0
–3
–2
–2
–2
–3
Preliminary
Max
25
25
25
25
25
25
25
25
25
25
25
25
28
25
25
25
25
IH
=V
t
2t
CLCL
t
t
CLCL
CLCL
t
CLCL
CC
CLCH
t
t
t
t
t
CLCH
CHCL
CLAX
CLCH
CLCH
+ t
– 0.5 V.
Min
–10=30
10
–10=30
15
15
–15=65
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–2=16
CHCL
25 MHz
=0
–2
–2
–2
–3
–3
Max
20
20
20
20
20
20
20
20
20
20
20
20
24
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns