ADR395 AD [Analog Devices], ADR395 Datasheet - Page 25

• Manufacturer Part Number: ADR395
• Description: Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 8). The data bits are in positions DB15 to DB0 for the AD5762R as shown in Table 11.
Table 11. Programming the AD5762R Data Register
REG2
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13.
Table 12. Programming the AD5762R Coarse Gain Register
Table 13. Output Range Selection
Output Range
±10 V (default)
±10.2564 V
±10.5263 V
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The AD5762R fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC
channel by −32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 14 and Table 15. The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos
complement.
Table 14. Programming AD5762R Fine Gain Register
Table 15. AD5762R Fine Gain Register Options
Gain Adjustment
+31 LSBs
+30 LSBs
No Adjustment (default)
−31 LSBs
−32 LSBs
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each
channel by −16 LSBs to +15.875 LSBs in steps of ⅛ LSB as shown in Table 16 and Table 17. The offset register coding is twos complement.
Table 16. Programming the AD5762R Offset Register
REG2
1
REG2
0
1
REG2
0
REG1
REG1
0
1
REG1
0
REG0
0
REG1
REG0
1
CG1
0
0
1
1
REG0
A2
DAC Address
0
CG0
0
1
0
A1
A2
DAC Address
A2
A0
REG0
A1
1
DAC Address
FG5
0
0
-
0
-
1
1
DB15
A0
A1
DB14
A2
DB15:DB8
Don’t Care
A0
DB13
FG4
1
1
-
0
-
0
0
DAC Address
Rev. PrA | Page 25 of 33
DB12
A1
DB15:DB6
Don’t Care
DB11
DB7
OF7
A0
FG3
1
1
-
0
-
0
0
DB10
DB6
OF6
DB9
16-Bit DAC Data
DB5
FG5
DB8
DB5
OF5
DB15 …. DB2
FG2
1
1
-
0
-
0
0
Don’t Care
DB7
DB4
FG4
DB4
OF4
DB6
DB3
FG3
DB5
DB3
OF3
FG1
1
1
-
0
-
0
0
DB4
DB2
FG2
DB2
OF2
DB1
CG1
DB3
DB1
DB2
AD5762R
FG1
DB1
OF1
FG0
1
0
-
0
-
1
0
DB1
DB0
CG0
DB0
OF0
DB0
FG0
DB0