ADR395 AD [Analog Devices], ADR395 Datasheet - Page 7

• Manufacturer Part Number: ADR395
• Description: Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
TIMING CHARACTERISTICS
AV
DV
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
Standalone mode only.
Measured with the load circuit of Figure 5.
Daisy-chain mode only.
4
5, 6
DD
CC
= 11.4 V to 16.5 V, AV
= 2.7 V to 5.25 V, R
1, 2, 3
LOAD
SS
Limit at T
33
13
13
13
13
40
2
5
1.4
400
10
500
10
10
2
25
13
2
170
= 10 kΩ, C
= −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external;
r
= t
f
= 5 ns (10% to 90% of DV
MIN
L
, T
= 200 pF. All specifications T
MAX
CC
) and timed from a voltage level of 1.2 V.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns max
µs max
ns min
µs max
ns max
ns min
µs min
ns min
Rev. PrA | Page 7 of 33
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
MIN
th
SCLK falling edge to SYNC rising edge
to T
MAX
, unless otherwise noted.
AD5762R