ADR435 AD [Analog Devices], ADR435 Datasheet - Page 12

• Manufacturer Part Number: ADR435
• Description: Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output
• Manufacturer: AD [Analog Devices]

AD5735
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
R
R
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DV
DGND
LDAC
CLEAR
SET_B
SET_A
DD
Description
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
I
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
I
Ground Reference Point for Internal Reference.
Ground Reference Point for Internal Reference.
Address Decode for the Device Under Test (DUT) on the Board.
Address Decode for the DUT on the Board.
Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked
into the input shift register on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface
operates at clock speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5).
Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V.
Digital Ground.
Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.
When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of
SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output
is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be
updated simultaneously. The LDAC pin must not be left unconnected.
Active High, Edge Sensitive Input. When this pin is asserted, the output current and voltage are set to the
programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information,
see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to.
OUT_B
OUT_A
INDICATOR
NOTES
1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE
AV
IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
REFGND
REFGND
temperature drift performance. For more information, see the External Current Setting Resistor section.
temperature drift performance. For more information, see the External Current Setting Resistor section.
CLEAR
R
R
ALERT
FAULT
SS
DGND
LDAC
SYNC
SCLK
SET_B
SET_A
DV
PIN 1
SDIN
SDO
AD0
AD1
PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
DD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Figure 7. Pin Configuration
Rev. B | Page 12 of 48
(Not to Scale)
AD5735
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMP
I
V
AV
SW
GNDSW
GNDSW
SW
AV
SW
GNDSW
GNDSW
SW
AGND
V
I
OUT_C
OUT_B
BOOST_C
BOOST_B
CC
SS
C
D
A
B
DCDC_C
C
D
A
B
Data Sheet