LTC1325 LINER [Linear Technology], LTC1325 Datasheet - Page 11

• Manufacturer Part Number: LTC1325
• Description: Microprocessor-Controlled Battery Management System
• Manufacturer: LINER [Linear Technology]

FUNCTIONAL DESCRIPTIO
Bit 13: Power Shutdown (PS)
PS selects between the normal operating mode, or the
shutdown mode.
Bits 14 to 16: Duty Ratio Select (DR0 to DR2)
DR2, DR1 and DR0 select the duty cycle of the charging
loop operation (not 111kHz PWM duty cycle). The last
three selections place the chip into a test mode and should
not be used.
Bit 17: Fail-Safe Latch Clear (FSCLR)
When FSCLR bit is set to one, the internal fail-safe timer is
reset to 0, and the fail-safe latches are reset. FSCLR is
automatically reset to 0 when CS goes high.
Bits 18 to 20: Timeout Period Select (TO0 to TO2)
TO2, TO1 and TO0 select the desired fail-safe timeout
period,t
DR2
TO2
FSCLR
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
U
PS
0
1
0
1
OUT
DR1
TO1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
. On power-up, the default timeout is 5 minutes.
U
DESCRIPTION
Normal Operation
Shutdown All Circuits Except Digital Inputs
DESCRIPTION
No Action
Reset Fail-Safe Timer and Latches
DR0
TO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
1/16
1/8
1/4
1/2
1
Test Mode 1
Test Mode 2
Test Mode 3
TIMEOUT (MINUTES)
5
10
20
40
80
160
320
Indefinite (No Timeout)
U
Bits 21 and 22: Charging Loop Reference Voltage
Select (VR0 and VR1)
VR1 and VR0 select the desired reference voltage V
for the charging loop. The charging loop will force the
average voltage at the Sense pin to be equal to V
average charging current is V
STATUS WORD
The status word is 8 bits long and contains the status of
the internal fail-safe circuits.
Bit 1: Battery Present (BATP)
The BATP bit = 1 indicates the presence of the battery. The
bit is set to 1 when the voltage at the V
(V
V
Bit 2: Battery Reversed (BATR) or Shorted
The BATR bit indicates when the battery is connected
backwards or shorted. The bit is set when the battery cell
voltage at the output of the battery divider V
100mV.
BAT
DD
BATR
BATP
VR1
0
0
1
1
0
1
0
1
is pulled high by R
– 1.8V). BATP = 0 when the battery is removed and
BATP
1
BATR
CONDITIONS
(V
V
CONDITIONS
V
V
2
VR0
BAT
CELL
CELL
0
1
0
1
DD
FMCV
– 1.8) < V
< (V
Figure 2. Status Word
> 100mV
< 100mV
3
DD
– 1.8)
FEDV
V
18
34
55
160
TRK
4
DAC
BAT
(see Figure 3).
(mV)
< V
FHTF
DAC
5
DD
/R
FLTF
SENSE
6
BAT
t
OUT
7
(see Figure 4).
LTC1325
pin falls below
CELL
LTC1325 • F02
FS
8
DAC
is below
11
CHRG
. The