LTC2171-14 LINER [Linear Technology], LTC2171-14 Datasheet - Page 15

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LTC2171-14

Manufacturer Part Number
LTC2171-14
Description
Quad 14-Bit, 125Msps ADC with Integrated Drivers
Manufacturer
LINER [Linear Technology]
Datasheet
applicaTions inForMaTion
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should be
treated as analog signals—do not route them next to digital
traces on the circuit board. There are two modes of opera-
tion for the encode inputs: the differential encode mode
(Figure 3), and the single-ended encode mode (Figure 4).
The differential encode mode is recommended for sinusoi-
dal, PECL, or LVDS encode inputs (Figure 5 and Figure 6).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
ENC
ENC
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
+
Figure 3. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1µF
0.1µF
LTM9012
Figure 5. Sinusoidal Encode Drive
15k
30k
T1
V
DD
50Ω
50Ω
V
DD
0.1µF
100Ω
DIFFERENTIAL
COMPARATOR
ENC
ENC –
+
9012 F03
LTM9012
9012 F05
above V
from 1.1V to 1.6V. In the differential encode mode, ENC
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
to ground and ENC
input. ENC
to 3.3V CMOS logic levels can be used. The ENC
is 0.9V. For good jitter performance ENC
rise and fall times.
DD
Figure 4. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
1.8V TO 3.3V
+
(up to 3.6V), and the common mode range is
Figure 6. PECL or LVDS Encode Drive
can be taken above V
PECL OR
CLOCK
LVDS
0V
+
+
should have fast rise and fall times.
is driven with a square wave encode
0.1µF
0.1µF
ENC
ENC
+
ENC
ENC
LTM9012
+
DD
30k
LTM9012
(up to 3.6V) so 1.8V
CMOS LOGIC
LTM9012
BUFFER
+
9012 F06
should have fast
9012 F04
is connected
+
threshold
15
9012f

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