LTC2171-14 LINER [Linear Technology], LTC2171-14 Datasheet - Page 17

• Manufacturer Part Number: LTC2171-14
• Description: Quad 14-Bit, 125Msps ADC with Integrated Drivers
• Manufacturer: LINER [Linear Technology]

applicaTions inForMaTion
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current is
doubled to maintain the same output voltage swing. In the
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
CHn
<–0.1000000V
(0.2V RANGE)
>0.1000000V
–0.0000122V
–0.0000244V
–0.0999878V
–0.1000000V
+0.0999878V
+0.0999756V
+0.0000122V
+0.0000000V
+
TO CHn
–
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0000
(OFFSET BINARY)
D13 TO D0
(2’s COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D13 TO D0
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
and all other bits. The FR and DCO outputs are not affected.
The output randomizer is enabled by serially programming
mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the test
patterns override all other formatting modes: 2’s comple-
ment and randomizer.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
power or enable in-circuit testing. When disabled the com-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
LTM9012
17
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