P620-00DC PLL [PhaseLink Corporation], P620-00DC Datasheet

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P620-00DC

Manufacturer Part Number
P620-00DC
Description
Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.)
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
DIE SPECIFICATIONS
FEATURES
DESCRIPTION
The PLL620-00 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
SEL
Pad dimensions
Vin
X+
X-
Reverse side
100MHz to 200MHz Fundamental or 3
Overtone Crystal input.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier) or 400 – 700MHz
(4x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
Thickness
Name
Size
Oscillator
Amplifier
PLL by-pass
Locked
(Phase
Loop)
PLL
Low Phase Noise XO with multipliers (for HF Fund. and 3
80 micron x 80 micron
62 x 65 mil
10 mil
Value
GND
PLL620-00
OE
Q
Q
rd
OUTPUT SELECTION AND ENABLE
DIE CONFIGURATION
Pad #9:
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad
Y
SEL3^
SEL2^
XOUT
OE_SELECT
CTRL
OUTSEL1
(Pad #18)
1 (Default)
XIN
(Pad #9)
OE
NC
X
(0,0)
0
0
1
1
0
Bond to GND to set to “0”, bond to VDD to set to “1”
#9) is “1”
Logical states defined by CMOS levels if OE_SELECT is
“0”
26
27
28
29
30
31
25
1
C502A
A1010-10A
24
2
OUTSEL0
(Pad #25)
Die ID:
1 (Default)
0 (Default)
OE_CTRL
(Pad #30)
23
3
0
1
0
1
22
0
1
4
21
5
65 mil
PLL620-00
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
20
Tri-state
Output enabled
Output enabled
Tri-state
Selected Output
6
19
7
State
18
8
rd
10
12
11
16
15
14
13
(1550,1475)
17
9
O.T.)
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^

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P620-00DC Summary of contents

Page 1

Low Phase Noise XO with multipliers (for HF Fund. and 3 FEATURES • 100MHz to 200MHz Fundamental or 3 Overtone Crystal input. • Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier) or 400 – 700MHz (4x ...

Page 2

Low Phase Noise XO with multipliers (for HF Fund. and 3 FREQUENCY SELECTION TABLE SEL3 SEL2 (Pad #28) (Pad #29 All pads have internal pull-ups (default value is 1). Bond to GND to set ...

Page 3

Low Phase Noise XO with multipliers (for HF Fund. and 3 4. Jitter Specifications PARAMETERS Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to- peak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter ...

Page 4

Low Phase Noise XO with multipliers (for HF Fund. and 3 7. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V Magnitude Change DD Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current ...

Page 5

Low Phase Noise XO with multipliers (for HF Fund. and 3 9. PECL Electrical Characteristics PARAMETERS SYMBOL Output High Voltage Output Low Voltage 10. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT 50Ω ...

Page 6

Low Phase Noise XO with multipliers (for HF Fund. and 3 PAD ASSIGNMENT Pad # Name 1 GND 2 GND 3 GND 4 GND 5 GND 6 N/C 7 GND 8 GNDBUF 9 OE_SELECT 10 LVDS 11 PECL 12 VDDBUF ...

Page 7

... President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 7 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL620- Marking P620-00DC PLL620-00 TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE Package Option Die – ...

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