LTC2205-14 LINER [Linear Technology], LTC2205-14 Datasheet - Page 15

• Manufacturer Part Number: LTC2205-14
• Description: 14-Bit, 65Msps ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2205-14 is a CMOS pipelined multi-step converter
with a front-end PGA. As shown in Figure 1, the converter
has fi ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205-14 has two phases of operation, determined
by the state of the differential ENC
brevity, the text will refer to ENC
ENC high and ENC
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and a residue amplifi er. In opera-
tion, the ADC quantizes the input to the stage, and the
quantized value is subtracted from the input by the DAC
to produce a residue. The residue is amplifi ed and output
by the residue amplifi er. Successive stages operate out
of phase so that when odd stages are outputting their
residue, the even stages are acquiring that residue and
vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifi er which
drives the fi rst pipelined ADC stage. The fi rst stage acquires
the output of the S/H amplifi er during the high phase of
ENC. When ENC goes back low, the fi rst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fi fth stage for fi nal evaluation.
+
less than ENC
+
+
–
greater than ENC
/ENC
as ENC low.
–
input pins. For
–
as
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2205-14
CMOS differential sample and hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(C
attached to each input (C
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors which charge to, and track the differential in-
put voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
ENC
ENC
A
A
IN
IN
SAMPLE
+
+
–
–
LTC2005-14
) through NMOS transitors. The capacitors shown
1.6V
1.6V
V
V
6k
6k
DD
DD
Figure 2. Equivalent Input Circuit
V
R
R
PARASITIC
PARASITIC
DD
3Ω
3Ω
PARASITIC
C
1.8pF
C
1.8pF
PARASITIC
PARASITIC
LTC2205-14
) are the summation of
20Ω
20Ω
R
R
ON
ON
C
C
SAMPLE
SAMPLE
4.9pF
4.9pF
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