LTC2205-14 LINER [Linear Technology], LTC2205-14 Datasheet - Page 16

• Manufacturer Part Number: LTC2205-14
• Description: 14-Bit, 65Msps ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2205-14
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specifi ed performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The V
to provide the common mode bias level. V
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The V
close to the ADC with 2.2µF or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2205-14 can be infl uenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can infl uence SFDR. At the falling edge of ENC the
sample-and-hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
incomplete settling may degrade the SFDR. The sampling
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ENCODE
); however, this is not always possible and the
CM
CM
pin must be bypassed to ground
output pin (Pin 2) is designed
CM
can be tied
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A fi rst order RC lowpass fi lter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2205-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC fi lter.
Figures 3, 4a and 4b show three examples of input RC
fi ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well as
noise coupled from the digital circuitry. The LTC2205-14
does not require any input fi lter to achieve data sheet
specifi cations; however, no fi ltering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2205-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with V
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50 can reduce
the input bandwidth and increase high frequency distor-
tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
or less for each input. The source
CM
, setting the ADC input
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