LTC3615 LINER [Linear Technology], LTC3615 Datasheet - Page 16

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LTC3615

Manufacturer Part Number
LTC3615
Description
Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter
Manufacturer
LINER [Linear Technology]
Datasheet

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LTC3615
applicaTions inForMaTion
of periods to settle until the frequency at SW matches the
frequency and phase of R
When the external clock signal is removed, the LTC3615
needs approximately 5µs to detect the absence of the
external clock. During this time, the PLL will continue to
provide clock cycles before it is switched back to the de-
fault frequency or selected frequency (set via the external
R
A safe way of driving the R
coupling to the clock generator via a 15pF capacitor. The AC
coupling avoids complications if the external clock genera-
tor cannot provide a continuous clock signal at the time of
start-up, operation and shut down of the LTC3615.
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is significantly different from the internal
default of 2.25MHz.
Phase Selection
Channel 2 will operate in-phase, 180° out-of-phase
(anti-phase) or shifted by 90° from channel 1 depending
on the state of the PHASE pin—low, midrail and high,
respectively. Antiphase generally reduces input voltage
and current ripple. Crosstalk between switch nodes SW1,
SW2 and components or sensitive lines connected to FBx,
ITHx, R
waveforms and unexpectedly large input and output volt-
age ripple.
The situation improves if rising and falling edges of the
switch nodes are timed carefully not to coincide. Depending
on the duty cycle of the two channels, choose the phase
difference between the channels to keep edges as far away
from each other as possible.

T
resistor).
V
IN
SV
R
T
T
LTC3615
/SYNC or SRLIM can cause unstable switching
/SYNC
IN
f
2.25MHz
SW
R
OSC
T
/SYNC.
0.4V
V
T
IN
/SYNC input is with an AC
SV
R
T
LTC3615
/SYNC
IN
SGND
Figure 4. Setting the Switching Frequency
f
SW
1/R
OSC
T
P
For a duty cycle of less than 40% for one channel and more
than 60% for the other channel, choose a phase shift of 0
or 180° (PHASE = SGND or SV
a duty cycle of around 50%, select a phase difference of
90° (PHASE = one-half SV
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆I
with higher inductance.
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆I
The largest ripple current occurs at the highest V
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower DC
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
1.2V
0.3V
V
IN
L
∆I
=
L
SV
R
T
LTC3615
IN
/SYNC
=
SGND
f
SW
f
SW
V
OUT
V
f
1/T
OUT
SW
L
I
P
L
L MAX
increases with higher V
(
15pF
)
1
IN
V
T
P
IN MAX
).
V
1
OUT
(
IN
1.2V
0.3V
V
). If both channels have
IN MAX
V
)
OUT
(
V
R
L
IN
T
= 0.3(I
IN
)
SV
R
 
T
LTC3615
/SYNC
IN
SGND
and decreases
OUT(MAX)
3615 F04
f
1/T
SW
IN
P
. To
3615f
).

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