LTC3615 LINER [Linear Technology], LTC3615 Datasheet - Page 9

• Manufacturer Part Number: LTC3615
• Description: Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter
• Manufacturer: LINER [Linear Technology]

pin FuncTions
PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to
SGND, the phase between SW1 and SW2 will be 0°. Tying
PHASE to SV
PHASE pin tied to half of the SV
shift will be selected.
V
nel 2. See V
ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of
Channel 2. See ITH1.
TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start, Ex-
ternal Reference Input for Channel 2. See TRACK/SS1.
SGND (Pin 5/Pin 8): Signal Ground. All small-signal and
compensation components should connect to this ground
pin which, in turn, should be connected to PGND at one
point.
PV
Input. See PV
SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node.
See SW1.
RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See
RUN1.
RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forc-
ing RUN1 above the input threshold enables the output
SW1 of channel 1. Forcing both RUNx pins to ground
shuts down the LTC3615. In shutdown, all functions
are disabled and the LTC3615 draws <1µA of supply
current.
R
pin provides three modes of setting the switching fre-
quency.
1. Connecting a resistor from R
2. Driving R
FB2
T
/SYNC (Pin 12/Pin 15): Oscillator Frequency. This
IN2
set the switching frequency based on the resistor
value.
synchronize the switcher to the applied frequency. The
(Pin 2/Pin 5): Voltage Feedback Input Pin for Chan-
(Pins 6, 7/Pins 9, 10) Channel 2 Power Supply
FB1
T
IN
IN1
/SYNC with an external clock signal will
.
will select 180° of phase shift. With the
.
(FE/UF)
IN
T
/SYNC to ground will
voltage, 90° of phase
3. Tying this pin to SV
PGOOD2 (Pin 13/Pin 16): Power Good Output for
Channel 2. See PGOOD1.
SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the
switch pins is programmed with the SRLIM pin:
1. Tying this pin to SGND selects maximum slew rate.
2. Minimum slew rate is selected when the pin is open.
3. Connecting a resistor from SRLIM to SGND allows the
4. If SRLIM is tied to SV
PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for
Channel 1. The open-drain output will be pulled down to
ground when the FB1 voltage of the channel is not within
the power good voltage window. The PGOOD1 will also be
pulled down if the channel is not enabled with the RUN1
pin or an undervoltage at SV
(SRLIM = SV
to the actual TRACK/SS pin voltage.
SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching
Node. Connection to the external inductor. This pin con-
nects to the drains of the internal synchronous power
MOSFET switches.
PV
Inputs. These pins connect to the source of the internal
power P-channel MOSFET of channel 1. P
are independent of each other. They may connect to equal
or lower supplies than S
SV
ers the internal control circuitry and is monitored by the
undervoltage lockout comparator.
slope compensation is automatically adapted to the
external clock frequency.
oscillator frequency.
slew rate to be continuously adjusted.
mum and DDR mode is enabled (see the Applications
Information section).
IN1
IN
(Pin 20/Pin 23) Signal Input Supply. This pin pow-
(Pins 18, 19/Pins 21, 22): Channel 1 Power Supply
IN
), the power good window moves in relation
IN
VIN
IN
enables the internal 2.25MHz
.
the slew rate is set to maxi-
IN
is detected. In DDR mode
LTC3615
VIN1
and P
VIN2

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