IDT71T75602 Integrated Device Technology, IDT71T75602 Datasheet

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IDT71T75602

Manufacturer Part Number
IDT71T75602
Description
512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
Manufacturer
Integrated Device Technology
Datasheet

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©2004 Integrated Device Technology, Inc.
R/
CLK
I/O
A
ADV/
TMS
TDI
TCK
TDO
ZZ
V
V
0
DD
SS
-A
0
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 225 MHz
(3.0 ns Clock-to-Data Access)
ZBT
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W W W W W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
1
1
-I/O
, CE
, V
,
19
DDQ
31
TM
2
, I/O
,
2
,
Feature - No dead cycles between write and read
P1
2
3
-I/O
,
P4
4
OE
OE
OE
OE
DDQ
BW
BW
BW
BW
)
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Linear / Interleaved Burst Order
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Advance burst address / Load new address
Test Mode Select
Test Data Input
Test Clock
Test Data Input
1
- BW
BW
BW
BW
BW
4
) control (May tie active)
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
1
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
Bus Turnaround.
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
Address and control signals are applied to the SRAM during one
The IDT71T75602/802 contain data I/O, address and control signal
A Clock Enable CEN pin allows operation of the IDT71T75602/802
There are three chip enable pins (CE
Supply
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
1
, CE
2
IDT71T75602
IDT71T75802
, CE
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Static
Static
Static
2
N/A
N/A
N/A
N/A
N/A
) that allow the
DSC-5313/08
TM
, or Zero
5313 tbl 01

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