IDT71T75602 Integrated Device Technology, IDT71T75602 Datasheet - Page 2

• Manufacturer Part Number: IDT71T75602
• Description: 512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
mode, the IDT71T75602/802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
The IDT71T75602/802 have an on-chip burst counter. In the burst
I/O
I/O
ADV/
Symbol
A
V
R/
P1
TMS
TCK
TDO
CE
CLK
V
V
0
1
0
TDI
1
ZZ
DDQ
-A
,
-I/O
DD
SS
-
-I/O
2
19
31
P4
4
2
Linear Burst Order
Test Mode Select
Data Input/Output
Test Data Output
Advance / Load
Address Inputs
Test Data Input
Individual Byte
Write Enables
Output Enable
Power Supply
Power Supply
Pin Function
Clock Enable
Chip Enables
Read / Write
Sleep Mode
Chip Enable
JTAG Reset
Test Clock
(Optional)
Ground
Clock
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/
ADV/
sampled lo w at the rising edge of clock with the chip selected. When ADV/
any burst in progress is terminated. When ADV/
for any burst that was in progress. The external addresses are ignored when ADV/
R/ signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When
ignored and outputs remain unchanged. The effect of
to high clock transition did not occur. For normal operation,
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/
high. The appropriate byte(s) of data are written into the device two cycles later.
always doing write to the entire 36-bit word.
Synchronous active low chip enable.
sampled high or CE
ZBT
Synchronous active high chip enable. CE
but otherwise identical to
This is the clock input to the IDT71T75602/802. Except for
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
by the rising edge of CLK.
Burst order selection input. When
Linear burst sequence is selected.
Asynchronous output enable.
are in a high-impedance state.
operation,
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
2.5V core power supply.
2.5V I/O Supply.
Ground.
TM
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
is a sync hronous input that is used to load the internal registers with new address and control when it is
low,
and ADV/
can be tied low.
low, and true chip enables.
2
6.42
sampled low) and ADV/
are sampled low) the appropriate byte write signal (
2
1
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA).
and
The IDT71T75602/802 SRAMs utilize IDT’s latest high-performance
must be low to read data from the 71T75602/802. When
does not need to be actively controlled for read and write cycles. In normal
2
.
is high the Interleaved burst sequence is selected. When
1
is a static input and it must not change during device operation.
2
and
is used with
is sampled high, all other synchronous inputs, including clock are
Commercial and Industrial Temperature Ranges
2
low at the rising edge of clock, initiates a deselect cycle. The
Description
are used with CE
is sampled high then the internal burst counter is advanced
1
and
sampled high on the device outputs is as if the low
, all timing references for the device are made with
must be sampled low at rising edge of clock.
2
2
to enable the chip. CE
to enable the IDT71T75602/802 (
is low with the chip deselected,
1
-
1
4
-
) must be valid. The byte
is sampled high.
4
2
can all be tied low if
has inverted polarity
is high the I/O pins
is sampled
can be left
is low the
1
5313 tbl 02
or
2