IDT71T75602 Integrated Device Technology, IDT71T75602 Datasheet - Page 8

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IDT71T75602

Manufacturer Part Number
IDT71T75602
Description
512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
Manufacturer
Integrated Device Technology
Datasheet

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NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTES:
1. This assumes CEN, CE
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Third Address
Third Address
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
(R/W, ADV/LD, BWx)
delay from the rising edge of clock.
I/O
CONTROL
ADDRESS
[0:31]
(A
CLOCK
DATA
CYCLE
0
, I/O P
- A
(1)
(1)
18
(2)
)
(2)
(2)
[1:4]
1
, CE
2
, CE
D/Q27
n+29
C29
A29
2
are all true.
D/Q28
n+30
C30
A30
A1
A1
0
0
0
0
1
1
1
1
Sequence 1
Sequence 1
D/Q29
n+31
C31
A31
LBO
A0
A0
0
0
0
0
1
1
1
1
D/Q30
n+32
C32
A32
6.42
LBO
8
A1
A1
0
0
0
0
1
1
1
1
Sequence 2
Sequence 2
D/Q31
n+33
C33
A33
A0
A0
0
0
0
0
1
1
1
1
Commercial and Industrial Temperature Ranges
D/Q32
n+34
C34
A34
A1
A1
0
0
0
0
1
1
1
1
Sequence 3
Sequence 3
D/Q33
n+35
C35
A35
A0
A0
0
0
0
0
1
1
1
1
D/Q34
n+36
A36
C36
A1
A1
0
0
0
0
1
1
1
1
Sequence 4
Sequence 4
5313drw 03
D/Q35
n+37
C37
A37
5313 tbl 10
A0
A0
5313 tbl 11
0
0
0
0
1
1
1
1
,

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