CDP68HC68T1D Intersil Corporation, CDP68HC68T1D Datasheet
CDP68HC68T1D
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CDP68HC68T1D Summary of contents
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... RAM and Power Sense/Control Pinouts CLKOUT CLK OUT Clock provides a Ordering Information PART NUMBER CDP68HC68T1E CDP68HC68T1D CDP68HC68T1M CDP68HC68T1M2 CDP68HC68T1W NOTE: Pin number references throughout this specification refer to the 16 lead PDIP/SBDIP/SOIC. See pinouts for cross reference. © Intersil Corporation 1999 1 CDP68HC68T1 (PDIP, SBDIP, SOIC) ...
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... Current Drain Per Input Pin Excluding V DD Current Drain Per Output Pin 40mA Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . +2.2V to +6.0V Temperature Range CDP68HC68T1D (SBDIP Package -55 CDP68HC68T1E (PDIP Package -40 CDP68HC68T1M/M2 (SOIC Packages -40 Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . (0 Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock Frequency ( +3.0V to +6.0V SCK CAUTION: Stresses above those listed in “ ...
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Static Electrical Specifications PARAMETER Operating Current (Note 5V Crystal Operation Standby Current (Note 2.2V B Crystal Operation Input Capacitance Maximum Rise and Fall Times (Except XTAL Input and POR ...
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Functional Block Diagram CE LINE 50/60Hz XTAL IN XTAL OUT OSCILLATOR PRESCALE V BATT PRESCALE SELECT CLOCK OUT CLOCK CONTROL REGISTER INT CLOCK AND V INTERRUPT DD INT CONTROL LOGIC V SS REGISTER LINE V POWER SYS INT STATUS SENSE ...
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RAM LOCATIONS 31 32 CLOCK/CALENDAR BYTES UNUSED 63 85 TEST MODE R = READABLE W = WRITABLE TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES ADDRESS LOCATION (H) FUNCTION 20 Seconds 21 Minutes 22 Hours 12 ...
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Programmers Model - Clock Registers HEX ADDRESS DB7 RAM DATA BYTE NOTE Don’t care writes when read. CDP68HC68T1 WRITE/READ REGISTERS DB0 TENS ...
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Functional Description The SPI real-time clock consists of a clock/calendar and RAM. Communications is established via the SPI (Serial Peripheral Interface) bus. In addition to the clock/cal- endar data from seconds to years, and system flexibility ...
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FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM FROM SYSTEM TO SYSTEM POWER POWER CONTROL V PSE SYS I CLK INTERRUPT OUT CONTROL REGISTER CPUR MISO SERIAL MOSI INTERFACE REAL-TIME CLOCK CDP68HC68T1 FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM Power Sensing (See ...
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V BATT V SYS SERIAL INTERFACE REAL-TIME CLOCK CDP68HC68T1 FIGURE 6. POWER-UP FUNCTIONAL DIAGRAM (INITIATED BY A RISE IN VOLTAGE ON THE “V CLK OUT Clock output pin. One of seven frequencies can be selected (or this output can be ...
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XTAL IN 22M T1 XTAL OUT C2 NOTES: 7. All frequencies recommended oscillator circuit. C1, C2 values crystal dependent used for 32KHz operation only. 100K - 300K range as specified by crystal manufacturer. FIGURE 7. OSCILLATOR CIRCUIT V ...
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Power Sense This bit is used to enable the line input pin to sense a power failure set high for this function. When power sense is selected, the input to the 50Hz to 60Hz prescaler is discon- nected. ...
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STATUS REGISTER (Read Only) - Address 30H WATCHDOG TEST MODE MODE CE DISABLE L RESET WRITE H READ H NOTES: 9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in ...
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CPOL bit in the microcomputer’s Control Register. A unique feature of the CDP68HC68T1 is that it automatically determines the level of the inactive clock by sampling SCK when CE becomes active (see Figure ...
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Read/Write Data (See Figure 10) Read/Write data follows the Address/Control byte. BIT CE SCK (NOTE) MOSI D7 MISO D7 NOTE: SCK can be either polarity. FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS Watchdog Reset - (See Figure 11) When watchdog operation ...
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CE SCK WRITE MOSI ADDRESS BYTE MOSI ADDRESS BYTE READ MISO FIGURE 12. SINGLE-BYTE TRANSFER WAVEFORMS CE SCK WRITE MOSI ADDRESS BYTE MOSI ADDRESS BYTE READ MISO DATA BYTE W/R ADDRESS DATA BYTE +1 DATA BYTE + (n-1) FIGURE 13. ...
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Dynamic Electrical Specifications IDENT. NO PARAMETER 1 Chip Enable Setup Time 2 Chip Enable After Clock Hold Time 3 Clock Width High 4 Clock Width Low 5 Data In to Clock Setup Time 7 Clock to Data Propagation Delay 8 ...
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Timing Diagrams 5 MOSI A6 W SCK 4 5 W/R MOSI MISO CE I SCK 4 System Diagrams AC BRIDGE LINE REGULATOR NOTE: Example of a system in which power is always on. Clock circuit driven by line ...
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System Diagrams (Continued) AC GENERATOR LINE NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal ...
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System Diagrams (Continued) AC REGULATOR LINE 0.1 R CHARGE 0.047 1k 20k RTC V DD FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP CDP68HC68T1 NC 100k POR SYS V BATT PSE XTAL CPUR V DD ...
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System Diagrams (Continued) CLOCK BUTTON IGNITION 5V REG + 12V - LINE V V BATT POR XTAL 2MHz V Example of an automotive system. The V switch is included to activate the system without turning on the ignition. Also, the ...
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Dual-In-Line Plastic Packages (PDIP) D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning ...
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Ceramic Dual-In-Line Metal Seal Packages (SBDIP) -A- - bbb BASE S2 PLANE -C- SEATING PLANE ccc ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - - 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the “MO ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...