CDP68HC68T1D Intersil Corporation, CDP68HC68T1D Datasheet - Page 14

• Manufacturer Part Number: CDP68HC68T1D
• Description: CMOS Serial Real-Time Clock With RAM and Power Sense/Control
• Manufacturer: Intersil Corporation

Read/Write Data (See Figure 10)
Read/Write data follows the Address/Control byte.
NOTE: SCK can be either polarity.
Watchdog Reset - (See Figure 11)
When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.
CPUR
SCK
CE
FIGURE 11. WATCHDOG OPERATION WAVEFORMS
SCK (NOTE)
MOSI
MISO
CE
SERVICE
TIME
D7
D7
BIT
FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS
D7
7
SERVICE
D6
D6
TIME
D6
6
D5
D5
CDP68HC68T1
D5
5
D4
D4
D4
14
4
Address And Data
Data transfers can occur one byte at a time (Figure 12) or in
a multibyte burst mode (Figure 13). After the Real-Time
Clock enabled, an Address/Control word is sent to set the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is trans-
ferred to or from the Clock Register or RAM location speci-
fied in the Address/Control byte and the Real-Time Clock is
then disabled. Write cycle causes the latched Clock Register
or RAM address to automatically increment. Incrementing
continues after each transfer until the device is disabled.
After incrementing to 1FH the address will “wrap” to 00H and
continue. Therefore, when the RAM is selected the address
will “wrap” to 00H and when the clock is selected the
address will “wrap” 20H.
D3
D3
D3
3
D2
D2
D2
2
D1
D1
D1
1
D0
D0
D0
0