CDP68HC68T1D Intersil Corporation, CDP68HC68T1D Datasheet - Page 13

• Manufacturer Part Number: CDP68HC68T1D
• Description: CMOS Serial Real-Time Clock With RAM and Power Sense/Control
• Manufacturer: Intersil Corporation

inactive clock polarity is determined by the CPOL bit in the
microcomputer’s Control Register. A unique feature of the
CDP68HC68T1 is that it automatically determines the level
of the inactive clock by sampling SCK when CE becomes
active (see Figure 8). Input data (MOSI) is latched internally
on the internal strobe edge and output data (MISO) is shifted
out on the shift edge, as defined by Figure 8. There is one
clock for each data bit transferred (address, as well as data
bits are transferred in groups of 8).
NOTE: “CPOL” is a bit that is set in the microcomputer’s Control
Register.
NOTE: SCK can be either polarity.
CPOL = 0
CPOL = 1
FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF
BIT
04
5
6
7
SCK (NOTE)
W/R
7
MOSI
CE
SCK
CE
SCK
MCU CLOCK POLARITY (CPOL)
MOSI
A0-A4
CLK RAM
0
W/R
CE
6
0
CLK RAM
FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS
W/R
SHIFT
SHIFT
5
MSB
INTERNAL
INTERNAL
0
STROBE
STROBE
Selects 5-Bit HEX Address of RAM or specifies Clock Register. Most Significant Address
Bit. If equal to “1”, A0 through A4 selects a Clock Register. If equal to “0”, A0 through A4
selects one of 32 RAM locations. Must be set to ”0” when not in Test Mode 7W/R W/R = “1”
initiates one or more WRITE cycles.W/R = “0”, initiates one or more READ cycles.
MSB -1
CLOCK
RAM
CDP68HC68T1
A4
4
A4
13
Address And Data Format
There are three types of serial transfer:
1. Address Control - Figure 9.
2. READ or WRITE Data - Figure 10.
3. Watchdog Reset (actually a non-transfer) Figure 11.
The Address/Control and Data bytes are shifted MSB first,
Into the serial data input (MOSI) and out of the serial data
output (MISO).
Any transfer of data requires an Address/Control byte to
specify a Write or Read operation and to select a Clock or
RAM location, followed by one or more bytes of data.
Data is transferred out of MISO for a Read and into MOSI for
a Write operation.
Address/Control Byte - Figure 9
It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then true
again. Bit 5 is used to select between Clock and RAM loca-
tions.
A3
A2
A3
3
A1
A2
2
A0
A1
1
A0
0