EPM2210 Altera Corporation, EPM2210 Datasheet - Page 43

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

Altera Corporation
December 2004
Slew-Rate Control
The output buffer for each MAX II device I/O pin has a programmable
output slew-rate control that can be configured for low noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal output delay to rising and falling edges.
The lower the voltage standard (e.g., 1.8-V LVTTL) the larger the output
delay when slow slew is enabled. Each I/O pin has an individual slew-
rate control, allowing the designer to specify the slew rate on a pin-by-pin
basis. The slew-rate control affects both the rising and falling edges.
Open-Drain Output
MAX II devices provide an optional open-drain (equivalent to open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write
enable signals) that can be asserted by any of several devices. This output
can also provide an additional wired-OR plane.
Programmable Ground Pins
Each unused I/O pin on MAX II devices can be used as an additional
ground pin. This programmable ground feature does not require the use
of the associated LEs in the device. In the Quartus II software, unused
pins can be set as programmable GND on a global default basis or they
can be individually assigned. Unused pins also have the option of being
set as tri-stated input pins.
Bus Hold
Each MAX II device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not necessary to hold a signal level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than V
overdriving signals. If the bus-hold feature is enabled, the device cannot
use the programmable pull-up option.
Core Version a.b.c variable
MAX II Device Handbook, Volume 1
CCIO
MAX II Architecture
to prevent
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