EPM2210 Altera Corporation, EPM2210 Datasheet - Page 60

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset
Circuitry
4–6
MAX II Device Handbook, Volume 1
I/O
MAX II devices have POR circuits to V
during power-up. The POR circuit monitors these voltages, triggering
download from the non-volatile configuration flash memory (CFM) block
to the SRAM logic, maintaining tri-state of the I/O pins (with weak pull-
up resistors enabled) before and during this process. When the MAX II
device enters user mode, the POR circuit releases the I/O pins to user
functionality and continues to monitor the V
a brown-out condition. If there is a V
operational level during user mode, the POR circuit resets the device and
re-triggers an SRAM download. The I/O bank V
monitored after initial power-up and transition into user mode
functionality.
Power-Up Characteristics
When power is applied to a MAX II device, the POR circuit monitors
V
1.55 V for MAX II G devices. From this voltage reference, SRAM
download and entry into user mode takes 200 to 450 µs maximum
depending on device density. This period of time is specified as t
the power-up timing section of Chapter 5. DC & Switching Characteristics.
CCINT
and begins SRAM download at a maximum voltage of 1.7 V, or
GND
Core Version a.b.c variable
Source
Drain
Drain
Source
PMOS
NMOS
Gate
Gate
P-Substrate
CCINT
CCINT
N+
N+
voltage sag below the MAX II
and V
CCINT
D
S
GND
I/O
G
CCIO
voltage level to detect
CCIO
levels are not
Altera Corporation
voltage levels
December 2004
CONFIG
in