Z80182 Zilog., Z80182 Datasheet - Page 23

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

Notes:
* The TEMT and THRE bits take on different functions when
† These signals are delayed to HOST when using character
DS971820600
Zilog
TEMT/Double Buffer mode is enabled.
emulation delay.
Error
Error in
RCVR
FIFO
*TEMT
† *THRE
Break
Detect
Framing
Error
Parity
Error
Overrun
Error
†Data
Ready
Description
At least one data byte available
in FIFO with one error
Transmitter empty
Transmitter holding
register is empty
Break occurs when
received data input
is held in logic-0
for longer than a
full word transmission
Received character
did not have a valid
stop bit
Received character
did not have correct
even or odd parity
Overlapping received
characters, thereby
destroying the
previous character
Indicates complete
incoming data has
been received
Table 6. 16550 Line Status Register
P R E L I M I N A R Y
How to Set
At least one error in receiver
FIFO
MPU writes a 1
When MPU has
read or emptied
the holding register
MPU writes 1
MPU writes 1
MPU writes 1
MPU makes
two writes
to receiver
buffer register
MPU writes to
RCVR FIFO or
receiver buffer
register
How to Clear
When there are no more
errors
MPU writes a 0
When holding register
is not empty
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
Empty Receiver
or Receiver FIFO
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
3-23