Z80182 Zilog., Z80182 Datasheet - Page 71

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

Although this bit is disabled by default, it is advised that
this bit is enabled to prevent interrupt conflict between
MIMIC and ESCC interrupts.
Interrupt Identification Register
Bit 7 and Bit 6 FIFO’s Enabled
These bits will read 1 if the FIFO mode is enabled on the
MIMIC.
Bit 5 and Bit 4 Always Read 0
Reserved bits.
b3
DS971820600
Zilog
0
0
1
0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
Figure 73. Interrupt Identification Register
b2
1
1
1
0
0
0
0
(PC Read Only, Address 02H)
b1
1
0
0
1
0
0
(Z180 MPU no access)
0
Priority
Highest
0
2nd
2nd
3rd
4th
0
0
0 if Interrupt Pending
Interrupt ID bit (0)
Interrupt ID bit (2)
Interrupt ID bit (1)
Always '0'
Always '0'
FIFO Enabled Flag
FIFO Enabled Flag
Interrupt Source
Overrun, Parity, Framing error
or Break detect bits set by MPU
Received Data trigger level
Receiver Timeout with data
in RCVR FIFO.
Transmitter Holding
Register Empty.
MODEM status: CTS,
DSR, RI or DCD
Table 19. Interrupt Identification Field
P R E L I M I N A R Y
Bits 3-1 Interrupt ID Bits
This 3-bit field is used to determine the highest priority
interrupt pending (see Table 19).
Bit 0 Interrupt Pending
This bit is logic 0 and interrupt is pending.
When the PC accesses the IIR, the contents of the register
and all pending interrupts are frozen. Any new interrupts
will be recorded, but not acknowledged, during the IIR
access.
(Z180 MPU Read/Write bits 6, 4, 3, 2, Address xxF5H)
D7 D6 D5 D4 D3 D2 D1 D0
0
0
Figure 74. Line Status Register
0
(PC Read Only, Address 05H)
RCVR FIFO drops below trigger level
Read RCVR FIFO
Writing to the Transmitter Holding
Register or reading the Interrupt
Identification Register when the
THRE is the source of the interrupt.
Reading the MODEM
status register.
INT Reset Control
Read Line Status Register
0
0
0
0
0
Z
ILOG
Data Ready
Overrun Error
Framing Error
Parity Error
Break Interrupt
THRE
TEMT
Error in RCVR FIFO
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
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