Z80182 Zilog., Z80182 Datasheet - Page 85

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

DS971820600
Address
Zilog
/IROQ
/WR
/RD
/TENDi
(At edge
0
(At level
/DREQi
/DREQi
sense)
sence)
ST
Ø
T1
DMA Control Signals
[
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
T2
28
9
I/O Read Cycle
TW
T1
17
[3]
Figure 93. DMA Control Signals
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
P R E L I M I N A R Y
Figure 92. CPU Timing
T3
47
T2
45
29
13
45
45
T1
[2]
Tw
I/O Write Cycle
T2
46
28
22
[1]
TW
T3
48
Z
ILOG
T3
I
NTELLIGENT
T1
18
25
[4]
Z80182/Z8L182
29
P
ERIPHERAL
3-85