MC68HC11E0 Motorola, MC68HC11E0 Datasheet - Page 27
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MC68HC11E0
Manufacturer Part Number
MC68HC11E0
Description
(MC68HC711E Series) M68HC11E Series Programming Reference Guide
Manufacturer
Motorola
Datasheet
1.MC68HC11E0.pdf
(60 pages)
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A/D Control/Status Register (ADCTL)
MOTOROLA
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
$103C
$103D
$103E
$103F
$103F
Addr.
Highest Priority I Bit Interrupt and
RAM and I/O Mapping Register
System Configuration Register
System Configuration Register
Miscellaneous Register
Figure 6. Register and Control Bit Assignments (Sheet 6 of 6)
Register Name
(CONFIG)
(CONFIG)
Reserved
(HPRIO)
Address:
CCF — Conversion Complete Flag
Bit 6 — Unimplemented
SCAN — Continuous Scan Control
MULT — Multiple Channel/Single Channel Control
(INIT)
Reset:
Read:
Write:
(3)
M68HC11E Series Programming Reference Guide
This bit is set after an A/D conversion cycle and cleared when ADCTL is
written.
Always reads 0
Reset:
Reset:
Reset:
Reset:
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
0 = Convert single channel selected
1 = Convert four channels in selected group
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$1030
Bit 7
CCF
0
I = Indeterminate after reset
RBOOT
RAM3
Bit 7
EE3
R
0
0
0
1
= Unimplemented
= Unimplemented
6
0
SMOD
RAM2
EE2
R
6
0
0
0
1
SCAN
RAM1
5
MDA
EE1
R
5
0
0
0
1
MULT
IRV(NE)
RAM0
4
EE0
R
R
4
0
0
0
1
Indeterminate after reset
= Reserved
CD
NOSEC
NOSEC
PSEL3
3
REG3
R
U
U
3
0
0
CC
NOCOP
NOCOP
2
PSEL2
U = Unaffected
REG2
M68HC11E Series Registers
R
U
U
1
0
2
ROMON
CB
PSEL1
M68HC11ERG/AD
REG1
1
R
1
1
0
1
1
PSEL0
EEON
EEON
REG0
Bit 0
Bit 0
CA
R
U
0
1
1
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