MBM29F160BE-55 FUJITSU [Fujitsu Component Limited.], MBM29F160BE-55 Datasheet - Page 17

• Manufacturer Part Number: MBM29F160BE-55
• Description: 16M (2M X 8/1M X 16) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

Byte/Word Programming
Chip Erase
Sector Erase
MBM29F160BE = D8H for 8 mode; MBM29F160TE = 22D2H and MBM29F160BE = 22D8H for 16 mode).
(See Tables 4.1 and 4.2.)
All manufactures and device codes will exhibit odd parity with DQ
The sector state (protection or unprotection) will be indicated by address XX02H for 16 (XX04H for 8).
Scanning the sector addresses (A
a logical “1” at device output DQ
mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The automatic programming operation is completed when the data on DQ
bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 19 illustrates the Embedded Program
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded
Erase
an all zero data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide
any controls or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
(See Figure 8.)
Figure 20 illustrates the Embedded Erase
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
TM
MBM29F160TE
Algorithm command sequence the device will automatically program and verify the entire memory for
7
is “1” (See Write Operation Status section.) at which time the device returns to read mode.
0
for a protected sector. The programming verification should be perform margin
19
, A
18
, A
-55/-70/-90
TM
17
, A
Algorithm using typical command strings and bus operations.
TM
16
Algorithm using typical command strings and bus operations.
, A
15
, A
14
, A
/MBM29F160BE
13
, and A
7
defined as the parity bit.
12
) while (A
7
is equivalent to data written to this
6
, A
1
, A
0
) = (0, 1, 0) will produce
-55/-70/-90
17