MBM29F160BE-55 FUJITSU [Fujitsu Component Limited.], MBM29F160BE-55 Datasheet - Page 23

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MBM29F160BE-55

Manufacturer Part Number
MBM29F160BE-55
Description
16M (2M X 8/1M X 16) BIT
Manufacturer
FUJITSU [Fujitsu Component Limited.]
Datasheet
Write Pulse “Glitch” Protection
Logical Inhibit
Power-up Write Inhibit
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
MBM29F160TE
-55/-70/-90
IL
and OE = V
IL
, CE = V
IH
/MBM29F160BE
will not accept commands on the rising edge of WE.
IH
, or WE = V
IH
. To initiate a write, CE and WE must
-55/-70/-90
23

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